TLC5617_05 Datasheet, PDF (4/21 Pages) Texas Instruments – PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range, V_DD = 5 V ± 5%,
V_ref (REFIN)= 2.048 V (unless otherwise noted)
static DAC specifications
EZS
EG
PSRR
PARAMETER
Resolution
Integral nonlinearity (INL), end point adjusted
Differential nonlinearity (DNL)
Zero-scale error (offset error at zero scale)
Zero-scale-error temperature coefficient
Gain error
Gain error temperature coefficient
Zero scale
Power-supply rejection ratio
Gain
Zero scale
Gain
TEST CONDITIONS
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
Vref(REFIN) = 2.048 V,
See Note 1
See Note 2
See Note 3
See Note 4
See Note 5
See Note 6
See Notes 7 and 8
Slow
Fast
MIN TYP MAX UNIT
10
bits
± 1 LSB
± 0.1 ± 0.5 LSB
± 3 LSB
3
ppm/°C
± 3 LSB
1
ppm/°C
80
80
dB
80
80
NOTES: 1. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
2. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal
1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin).
5. Gain error is the deviation from the ideal output (Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
6. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin).
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.
OUT A and OUT B output specifications
VO
IOSC
IO(sink)
IO(source)
PARAMETER
Voltage output
Output load regulation accuracy
Output short circuit current
Output sink current
Output source current
TEST CONDITIONS
RL = 10 kΩ
VO(OUT) = 2V, RL from 10 kΩ to 2 kΩ
VO(OUT _A) or VO(OUT _B) to VDD or AGND
VO(OUT) > 0.25 V
VO(OUT) < 4.75 V
MIN TYP MAX UNIT
0
VDD –0.4 V
0.5
LSB
20
mA
5
mA
5
mA
reference input (REFIN)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
VI
Input voltage
Ri
Input resistance
Ci
Input capacitance
Reference feedthrough
REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9)
0
VDD – 2 V
10
MΩ
5
pF
– 80
dB
Reference input bandwidth (f–3dB)
REFIN = 0.2 Vpp + 1.024 V dc
Slow
Fast
0.5
MHz
1
NOTE 9: Reference feedthrough is measured at the DAC output with an input code = 00 hex and a Vref(REFIN) input = 1.024 V dc + 1 Vpp
at 1 kHz.
4
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