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TLC5617_05 Datasheet, PDF (12/21 Pages) Texas Instruments – PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS | |||
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TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B â JULY 1997 â REVISED MARCH 2000
APPLICATION INFORMATION
buffer amplifier
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-k⦠load with a 100-pF
load capacitance. Settling time is a software selectable 12.5 µs or 2.5 µs typical to within ±0.5 LSB of the final
value.
external reference
The reference voltage input is buffered which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 M⦠and the REFIN input capacitance is typically 5 pF, independent of input
code. The reference voltage determines the DAC full-scale output.
logic interface
The logic inputs function with CMOS logic levels. Most of the standard high-speed CMOS logic families may
be used.
serial clock and update rate
Figure 1 shows the TLC5617 timing. The maximum serial clock rate is
+ Ç Ç ) Ç Ç + f(SCLK)max
1
tw CH min tw CL min
20 MHz
+ Ç Ç Ç ) Ç ÇÇ ) Ç Ç The digital update rate is limited by the chip-select period, which is
tp(CS) 16 tw CH tw CL
tsu CS1
This equals 820-ns or 1.21-MHz update rate. However, the DAC settling time to 10 bits limits the update rate
for full-scale input step transitions.
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