TCAN1042-Q1 Datasheet, PDF (5/32 Pages) Texas Instruments – Automotive Fault Protected CAN Tranceiver

www.ti.com
7.3 Recommended Operating Conditions
V_CC
V_IO
I_OH(RXD)
I_OL(RXD)
5V Bus Supply Voltage Range
I/O Level Shifting Voltage Range
RXD terminal HIGH level output current
RXD terminal LOW level output current
TCAN1042-Q1, TCAN1042V-Q1, TCAN1042H-Q1
TCAN1042HV-Q1, TCAN1042G-Q1, TCAN1042GV-Q1
TCAN1042HG-Q1, TCAN1042HGV-Q1
SLLSES9 – FEBRUARY 2016
MIN MAX UNIT
4.5 5.5
V
3 5.5
–2
mA
2
7.4 Thermal Information
THERMAL METRIC⁽¹⁾
R_θJA
R_θJB
R_θJC(TOP)
Ψ_JT
Ψ_JB
Junction-to-air thermal resistance
Junction-to-board thermal resistance⁽³⁾
Junction-to-case (top) thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
P_D
Average power dissipation
Thermal shutdown temperature
Thermal shutdown hysteresis
TCAN1042-Q1
TEST CONDITIONS
D (SOIC)
High-K thermal resistance⁽²⁾
8 Pins
105.8
46.8
48.3
8.7
46.2
V_CC = 5 V, V_RXD = 5 V, T_J = 27°C, R_L = 60 Ω,
STB at 0 V, Input to TXD at 250 kHz, 25% duty
cycle square wave, C_{L_RXD} = 15 pF. Typical CAN
115
operating conditions at 500kbps with 25%
transmission (dominant) rate.
V_CC = 5.5 V, V_RXD = 5.5 V, T_J = 150°C, R_L = 50 Ω,
STB at 0 V, Input to TXD at 500 kHz, 50% duty
cycle square wave, C_{L_RXD} = 15 pF. Typical high
load CAN operating conditions at 1 Mbps with
268
50% transmission (dominant) rate and loaded
network.
170
5
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
mW
°C
°C
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-top characterization parameter, Ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, Ψ_JB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
Copyright © 2016, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: TCAN1042-Q1 TCAN1042V-Q1 TCAN1042H-Q1 TCAN1042HV-Q1 TCAN1042G-Q1
TCAN1042GV-Q1 TCAN1042HG-Q1 TCAN1042HGV-Q1