LMH6521 Datasheet, PDF (5/24 Pages) Texas Instruments – LMH6521 High Performance Dual DVGA

Symbol
Parameter
Conditions
Gain Accuracy
Gain Step Size
Channel Gain Matching
ChA - ChB, any gain setting
Channel Phase Matching
Cumulative Gain Error
0 to 12 dB attenuation setting
0 to 24 dB attenuation setting
0 to 31 dB attenuation setting
Cumulative Phase Shift
0 to 12 dB attenuation setting
0 to 24 dB attenuation setting
0 to 31 dB attenuation setting
Gain Step Switching Time
Gain Temperature Sensitivity
0 attenuation setting
Power Requirements
VCC
Supply Voltage
ICC
Supply Current
Both Channels Enabled
ICC
Disabled Supply Current
Both Channels
All Digital Inputs
Logic Compatibility
TTL, 2.5V CMOS, 3.3V CMOS
VIL
Logic Input Low Voltage
VIH
Logic Input High Voltage
IIH
Logic Input High Input Current Digital Input Voltage = 5V
IIL
Logic Input Low Input Current
Digital Input Voltage = 0V
Parallel and Pulse Mode Timing
t_GS
Setup Time
t_GH
Hold Time
t_LP
Latch Low Pulse Width
t_PG
Pulse Gap between Pulses
t_PW
Minimum Pulse Width
Pulse Mode
t_RW
Reset Width
Serial Mode Timing and AC Characteristics
SPI Compatible
f_SCLK
t_PH
t_PL
t_SU
t_H
t_OZD
Max Serial Clock Frequency
SCLK High State Duty Cycle
SCLK Low State Duty Cycle
Serial Data In Setup Time
Serial Data In Hold Time
Serial Data Out TRI-STATE-to-
Driven Time
% of SCLK Period
% of SCLK Period
Referenced to Negative edge of SCLK
t_OD
Serial Data Out Output Delay Time Referenced to Negative edge of SCLK
t_CSS
Serial Chip Select Setup Time Referenced to Positive edge of SCLK
Min
(Note 6)
Typ
(Note 5)
1
0.5
±0.04
±0.45
±0.1
±0.3
±0.5
±0.6
±5.3
±16.5
15
2.7
Max
(Note 6)
Units
%
dB
dB
degrees
dB
dB
dB
degrees
degrees
degrees
ns
mdB/°C
4.75
5.0
5.25
V
225
245
mA
35
mA
0.5
V
1.8
V
200
μA
–60
μA
3
ns
3
ns
7
ns
20
ns
15
ns
10
ns
50
MHz
50
%
50
%
2
ns
2
ns
10
ns
10
ns
5
ns
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