LMH6521 Datasheet, PDF (19/24 Pages) Texas Instruments – LMH6521 High Performance Dual DVGA

quickly adjusted either up or down one step at a time by a
negative pulse on the UP or DN pins. As shown in Figure 15
each gain step pulse must have a logic high state of at least
t_PW= 20 ns and a logic low state of at least t_PG= 20 ns for the
pulse to register as a gain change signal.
FIGURE 14.
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To provide a known gain state there is a reset feature in pulse
mode. To reset the gain to maximum gain both the UP and
DN pins must be strobed low together as shown in Figure
15. There must be an overlap of at least t_RW= 20 ns for the
reset to register.
design techniques assisted with the heat dissipation of the
LMH6521 to optimize distortion performance. Please refer to
the LMH6521EVAL evaluation board application note AN–
2045 for suggested layout techniques.
Package information is available on the National web site.
http://www.national.com/packaging/folders/SQA32A.html
INTERFACE TO ADC
The LMH6521 was designed to be used with National
Semiconductor's high speed ADC's. As shown in Figure 1, AC
coupling provides the best flexibility especially for IF sub-
sampling applications.
The inputs of the LMH6521 will self bias to the optimum volt-
age for normal operation. The internal bias voltage for the
inputs is approximately mid rail which is 2.5V with the typical
5V power supply condition. In most applications the LMH6521
input will need to be AC coupled.
The LMH6521 output common mode voltage is biased to 0V
and has a maximum differential output voltage swing of
10V_PPD as shown in Figure 16. This means that for driving
most ADCs AC coupling is required. Since most often a band
pass filter is desired between the amplifier and ADC the band-
pass filter can be configured to block the DC voltage of the
amplifier output from the ADC input. Figure 17 shows a wide-
band bandpass filter configuration that could be designed for
a 200Ω impedance system for various IF frequencies.
FIGURE 15. Pulse Mode Timing
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THERMAL MANAGEMENT
The LMH6521 is packaged in a thermally enhanced LLP
package and features an exposed pad that is connected to
the GND pins. It is recommended that the exposed pad be
attached directly to a large power supply ground plane for
maximum heat dissipation. The thermal advantage of the LLP
package is fully realized only when the exposed die attach
pad is soldered down to a thermal land on the PCB board with
the through vias planted underneath the thermal land. The
thermal land can be connected to any ground plane within the
PCB. However, it is also very important to maintain good high
speed layout practices when designing a system board.
The LMH6521EVAL evaluation board implemented an eight
metal layer pcb with (a) 4 oz. copper inner ground planes (b)
additonal through vias and (c) maximum bottom layer metal
coverage to assist with device heat dissipation. These pcb
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FIGURE 16. Output Voltage with Respect to Output
Common Mode
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FIGURE 17. Wideband Bandpass Filter
18
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