LMH6521 Datasheet, PDF (16/24 Pages) Texas Instruments – LMH6521 High Performance Dual DVGA

30120118
FIGURE 8. Parallel Mode Connection Not Using Latch
Pins (Latch pins tied to logic low state)
30120119
FIGURE 9. Parallel Mode Connection Using Latch Pins to
Mulitplex Digital Data
SERIAL MODE — SPI™ COMPATIBLE INTERFACE
(MOD1= 1, MOD0 = 0)
Serial interface allows a great deal of flexibility in gain pro-
gramming and reduced board complexity. Using only 4 wires
for both channels allows for significant board space savings.
The trade off for this reduced board complexity is slower re-
sponse time in gain state changes. For systems where gain
is changed only infrequently or where only slow gain changes
are required serial mode is the best choice. Refer to Digital
Control Mode Pin Functions table for pin definitions of the
LMH6521 in serial mode.
The serial interface is a generic 4-wire synchronous interface
that is compatible with SPI standard interfaces and used on
many microcontrollers and DSP controllers.
The serial mode is active when the two mode pins are set as
follows: MOD1=1, MOD0=0). In this configuration the pins
function as shown in the Pin Descriptions table. The SPI in-
terface uses the following signals: clock input (CLK), serial
data in (SDI), serial data out, and serial chip select (CS)
ENA and ENB pins are active in serial mode. For fast disable
capability these pins can be used and the serial register will
hold the last active gain state. These pins will float high and
can be left disconnected for serial mode. The serial control
bus can also disable the DVGA channels, but at a much slow-
er speed. The serial enable function is an AND function. For
a channel to be active both the enable pin and the serial con-
trol register must be in the enabled state. To disable a channel
either method will suffice. See the Typical Performance sec-
tion for disable and enable timing information.
LATA and LATB pins are not active during serial mode.
The serial clock pin CLK is used to register the input data that
is presented on the SDI pin on the rising edge; and to source
the output data on the SDO pin on the falling edge. User may
disable clock and hold it in the low state, as long as the clock
pulse-width minimum specification is not violated when the
clock is enabled or disabled.
The chip select pin CS starts a new register access with each
assertion - i.e., the SDATA field protocol is required. The user
is required to deassert this signal after the 16th clock. If the
SCSb is deasserted before the 16th clock, no address or data
write will occur. The rising edge captures the address just
shifted-in and, in the case of a write operation, writes the ad-
dressed register. There is a minimum pulse-width require-
ment for the deasserted pulse - which is specified in the
Electrical Specifications section.
SDI is an input pin for the serial data. It must observe setup/
hold requirements with respect to the SCLK. Each cycle is 16-
bits long
SDO is the data output pin and is normally at TRI-STATE^®
and is driven only when SCSb is asserted. Upon SCSb as-
sertion, contents of the register addressed during the first byte
are shifted out with the second 8 SCLK falling edges. Upon
power-up, the default register address is 00h
The SDO internal driver circuit is an open collector device with
a weak pull-up resistor to an internal 2.5V reference. It is 5V
tolerant so an external pull-up resistor can connect to 2.5V,
3.3V or 5V as shown in Figure 11. However, the external pull-
up resistor should be chosen to limit the current to 11mA or
less. Otherwise the SDO logic low output level (V_OL may not
achieve close to ground and in extreme case could cause
problem for FPGA input gate. Using minimum values for ex-
ternal pull-up resistor is a good to maximize speed for SDO
signal. So if high SPI clock frequency is needed then minimum
value external pull-up resistor is the best choice as shown in
Figure 11.
Each serial interface access cycle is exactly 16 bits long as
shown in Figure 10. Each signal's function is described below.
The read timing is shown in Figure 12, while the write timing
is shown in figure Figure 13.
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