LMH6521 Datasheet, PDF (15/24 Pages) Texas Instruments – LMH6521 High Performance Dual DVGA

FIGURE 5. Example Output Configuration
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The outputs of the LMH6521 need to be biased to near ground
potential. On the evaluation board, 1µH inductors are installed
to provide proper output biasing. The bias current is approx-
imately 36mA per output pin and is not a function of the load
condition, which makes the LMH6521 robust to handle vari-
ous output load conditions while maintaining superior linearity
as shown in Figure 6. With large inductors and high operating
frequencies the inductor will present a very high impedance
and will have minimal AC current. If the inductor is chosen to
have a smaller value, or if the operating frequency is very low
there could be enough AC current flowing in the inductor to
become significant. Make sure to check the inductor
datasheet to not exceed the maximum current limit.
60
40
50
VOUT = 4 VPP
36
40
32
30
28
Power Gain
20
24
10
20
Maximum Gain
f = 200 MHz
0
16
50 100 150 200 250 300
FILTER DIFFERENTIAL INPUT RESISTANCE (Ω)
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FIGURE 6. OIP3 vs Amplifier Load Resistance
DIGITAL CONTROL
The LMH6521 will support three modes of gain control, par-
allel mode, serial mode (SPI compatible) and pulse mode.
Parallel mode is fastest and requires the most board space
for logic line routing. Serial mode is compatible with existing
SPI compatible systems. The pulse mode is both fast and
compact, but must step through intermediate gain steps when
making large gain changes.
Pins MOD0 and MOD1 are used to configure the LMH6521
for the three gain control modes. MOD0 and MOD1 have
weak pull-up resistors to an internal 2.5V reference but is de-
signed for 2.5V-5V CMOS logic levels. MOD0 and MOD1 can
be externally driven (LOGIC HIGH) to voltages between 2.5V
to 5V to configure the LMH6521 into one of the three digital
control modes. Some pins on the LMH6521 have different
functions depending on the digital control mode. These func-
tions are shown in the Digital Control Mode Pin Functions
table.
PARALLEL MODE (MOD1= 1, MOD0 = 1)
When designing a system that requires very fast gain
changes parallel mode is the best selection. Refer to Digital
Control Mode Pin Functions table for pin definitions of the
LMH6521 in parallel mode.
The LMH6521 has a 6-bit gain control bus as well as latch
pins LATA and LATB for channels A and B. When the latch
pin is low, data from the gain control pins is immediately sent
to the gain circuit (i.e. gain is changed immediately). When
the latch pin transitions high the current gain state is held and
subsequent changes to the gain set pins are ignored. To min-
imize gain change glitches multiple gain control pins should
not change while the latch pin is low. Gain glitches could result
from timing skew between the gain set bits. This is especially
the case when a small gain change requires a change in state
of three or more gain control pins. If continuous gain control
is desired the latch pin can be tied to ground. This state is
called transparent mode and the gain pins are always active.
In this state the timing of the gain pin logic transitions should
be planned carefully to avoid undesirable transients
ENA and ENB pins are provided to reduce power consump-
tion by disabling the highest power portions of the LMH6521.
The gain register will preserve the last active gain setting dur-
ing the disabled state. These pins will float high and can be
left disconnected if they won't be used. If the pins are left dis-
connected a 0.01uF capacitor to ground will help prevent
external noise from coupling into these pins.
Figure 7, Figure 8, and Figure 9 show the various connections
in parallel mode with respect to the latch pin.
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FIGURE 7. Parallel Mode Connection for Fastest
Response
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