DS91C180_13 Datasheet, PDF (5/18 Pages) Texas Instruments – 100 MHz M-LVDS Line Driver/Receiver Pair

DS91C180, DS91D180
www.ti.com
SNLS158M – MARCH 2006 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. ^(1)(2)(3)(4)
Symbol
Parameter
Conditions
Min
C_A/B,
C_Y/Z
Receiver input or driver output capacitance balance
(C_A/C_B or C_Y/C_Z)
SUPPLY CURRENT (V_CC)
I_CCD
Driver Supply Current
I_CCZ
TRI-STATE Supply Current
I_CCR
Receiver Supply Current
I_CCB
Supply Current, Driver and Receiver Enabled
R_L = 50Ω, DE = V_CC, RE = V_CC
DE = GND, RE = V_CC
DE = GND, RE = GND
DE = V_CC, RE = GND
Typ Max Units
1.0
17 29.5 mA
7
9.0 mA
14 18.5 mA
20 29.5 mA
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. ^{(1) (2)}
Symbol
Parameter
Conditions
Min Typ Max Units
DRIVER AC SPECIFICATION
t_PLH
Differential Propagation Delay Low to High
t_PHL
t_SKD1 (t_sk(p))
t_SKD3
t_TLH (t_r)
t_THL (t_f)
Differential Propagation Delay High to Low
Pulse Skew |t_PLHD − t_PHLD| ^{(3) (4)}
Part-to-Part Skew ^{(5) (4)}
Rise Time ⁽⁴⁾
Fall Time ⁽⁴⁾
t_PZH
Enable Time (Z to Active High)
t_PZL
Enable Time (Z to Active Low )
t_PLZ
Disable Time (Active Low to Z)
t_PHZ
Disable Time (Active High to Z)
t_JIT
Random Jitter, RJ ⁽⁴⁾
f_MAX
Maximum Data Rate
RECEIVER AC SPECIFICATION
R_L = 50Ω, C_L = 5 pF,
C_D = 0.5 pF
Figure 8 and Figure 9
R_L = 50Ω, C_L = 5 pF,
C_D = 0.5 pF
Figure 10 and Figure 11
100MHz clock pattern⁽⁶⁾
1.0 3.4 5.5 ns
1.0 3.1 5.5 ns
300 420 ps
1.9 ns
1.0 1.8 3.0 ns
1.0 1.8 3.0 ns
8
ns
8
ns
8
ns
8
ns
2.5 5.5 psrms
200
Mbps
t_PLH
t_PHL
t_SKD1 (t_sk(p))
t_SKD3
t_TLH (t_r)
t_THL (t_f)
t_PZH
t_PZL
t_PLZ
t_PHZ
f_MAX
Propagation Delay Low to High
Propagation Delay High to Low
Pulse Skew |t_PLHD − t_PHLD|⁽³⁾⁽⁴⁾
Part-to-Part Skew ⁽⁵⁾⁽⁴⁾
Rise Time⁽⁴⁾
Fall Time⁽⁴⁾
Enable Time (Z to Active High)
Enable Time (Z to Active Low)
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
Maximum Data Rate
C_L = 15 pF
Figure 12 Figure 13 and Figure 14
R_L = 500Ω, C_L = 15 pF
Figure 15 and Figure 16
2.0 4.7 7.5 ns
2.0 5.3 7.5 ns
0.6 1.9 ns
1.5 ns
0.5 1.2 3.0 ns
0.5 1.2 3.0 ns
10
ns
10
ns
10
ns
10
ns
200
Mbps
(1) All typicals are given for V = 3.3V and T_A = 25°C.
(2) C_L includes fixture capacitance and C_D includes probe capacitance.
(3) t_SKD1, |t_PLHD − t_PHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(4) Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
(5) t_SKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same V_CC and within 5°C of each other within the operating temperature range.
(6) Stimulus and fixture jitter has been subtracted.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DS91C180 DS91D180