DS91C180_13 Datasheet, PDF (3/18 Pages) Texas Instruments – 100 MHz M-LVDS Line Driver/Receiver Pair

DS91C180, DS91D180
www.ti.com
SNLS158M – MARCH 2006 – REVISED APRIL 2013
Absolute Maximum Ratings ⁽¹⁾⁽²⁾
Supply Voltage, V_CC
Control Input Voltages
Driver Input Voltage
Driver Output Voltages
Receiver Input Voltages
Receiver Output Voltage
Maximum Package Power Dissipation at +25°C
Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 4 seconds)
ESD Ratings:
SOIC Package
Derate SOIC Package
θ_JA
θ_JC
(HBM 1.5kΩ, 100pF)
(EIAJ 0Ω, 200pF)
(CDM 0Ω, 0pF)
−0.3V to +4V
−0.3V to (V_CC + 0.3V)
−0.3V to (V_CC + 0.3V)
−1.8V to +4.1V
−1.8V to +4.1V
−0.3V to (V_CC + 0.3V)
1.1 W
8.8 mW/°C above +25°C
113.7 °C/W
36.9 °C/W
150°C
−65°C to +150°C
260°C
≥ 5 kV
≥ 250 V
≥ 1000 V
(1) “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be ensured. They are not meant to imply that the
device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
Supply Voltage, V_CC
Voltage at Any Bus Terminal (Separate or Common-Mode)
Differential Input Voltage V_ID
High Level Input Voltage V_IH
Low Level Input Voltage V_IL
Operating Free Air Temperature T_A
Min
Typ
Max
Units
3.0
3.3
3.6
V
−1.4
+3.8
V
2.4
V
2.0
V_CC
V
0
0.8
V
−40
+25
+85
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. ^(1)(2)(3)(4)
Symbol
Parameter
Conditions
Min Typ Max Units
M-LVDS Driver
|V_YZ|
ΔV_YZ
Differential output voltage magnitude
Change in differential output voltage magnitude
between logic states
R_L = 50Ω, C_L = 5pF
Figure 3 and Figure 5
480
650 mV
−50
0
+50 mV
V_OS(SS)
|ΔV_OS(SS)|
Steady-state common-mode output voltage
R_L = 50Ω, C_L = 5pF
Change in steady-state common-mode output voltage ^{Figure 3 and Figure 4}
between logic states
0.3
1.8 2.1
V
0
+50 mV
V_OS(PP)
V_Y(OC)
V_Z(OC)
V_P(H)
V_P(L)
Peak-to-peak common-mode output voltage
Maximum steady-state open-circuit output voltage
Maximum steady-state open-circuit output voltage
Voltage overshoot, low-to-high level output
Voltage overshoot, high-to-low level output
(V_OS(pp) @ 500KHz clock)
Figure 6
R_L = 50Ω, C_L = 5pF,
C_D = 0.5pF
Figure 8 and Figure 9⁽⁵⁾
143
mV
0
2.4
V
0
2.4
V
1.2V_SS V
−0.2V_SS
V
I_IH
High-level input current (LVTTL inputs)
V_IH = 2.0V
-15
15
μA
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
(2) All typicals are given for V_CC = 3.3V and T_A = 25°C.
(3) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
(4) C_L includes fixture capacitance and C_D includes probe capacitance.
(5) Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
Copyright © 2006–2013, Texas Instruments Incorporated
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