DS90LV027A_16 Datasheet, PDF (5/21 Pages) Texas Instruments – LVDS Dual High Speed Differential Driver

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DS90LV027A
SNLS026D – MARCH 2000 – REVISED JUNE 2016
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾
PARAMETER
TEST CONDITIONS
MIN TYP⁽³⁾ MAX UNIT
V_OD
ΔV_OD
V_OH
V_OL
V_OS
ΔV_OS
I_OXD
I_OSD
V_IH
V_IL
I_IH
I_IL
V_CL
I_CC
Output differential voltage
V_OD magnitude change
Output high voltage
Output low voltage
Offset voltage
Offset magnitude change
Power-off leakage
Output short-circuit current
Input high voltage
Input low voltage
Input high current
Input low current
Input clamp voltage
Power supply current
R_L = 100 Ω (see Figure 15), DO+, DO− pins
R_L = 100 Ω (see Figure 15), DO+, DO− pins
R_L = 100 Ω (see Figure 15), DO+, DO− pins
R_L = 100 Ω (see Figure 15), DO+, DO− pins
R_L = 100 Ω (see Figure 15), DO+, DO− pins
R_L = 100 Ω (see Figure 15), DO+, DO− pins
V_OUT = V_CC or GND, V_CC = 0 V, DO+, DO− pins
DO+, DO− pins
DI pin
DI pin
V_IN = 3.3 V or 2.4 V, DI pin
V_IN = GND or 0.5 V, DI pin
I_CL = −18 mA, DI pin
V_IN = V_CC or GND, V_CC pin
No load
R_L = 100 Ω
250
0.9
1.125
0
2
GND
–1.5
360
450 mV
1
35 mV
1.4
1.6 V
1.1
V
1.2 1.375 V
3
25 mV
±1
±10 μA
–5.7
–8 mA
V_CC
V
0.8 V
±2
±10 μA
±1
±10 μA
–0.6
V
8
14
mA
14
20
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except V_OD.
(2) The DS90LV027A is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers
outputs.
(3) All typicals are given for: V_CC = 3.3 V and T_A = 25°C.
6.6 Switching Characteristics
R_L = 100 Ω and C_L = 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)^(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN TYP⁽⁴⁾ MAX UNIT
t_PHLD
t_PLHD
t_SKD1
t_SKD2
t_SKD3
t_SKD4
t_TLH
t_THL
f_MAX
Differential propagation delay high to low
Differential propagation delay low to high
Differential pulse skew |t_PHLD − t_PLHD|⁽⁵⁾
Channel to channel skew⁽⁶⁾
Differential part to part skew⁽⁷⁾
Differential part to part skew⁽⁸⁾
Transition low to high time
Transition high to low time
Maximum operating frequency⁽⁹⁾
0.3
0.8
0.3
1.1
0
0.3
0
0.4
0
0
0.2
0.5
0.2
0.5
350
1.5 ns
1.5 ns
0.7 ns
0.8 ns
1 ns
1.2 ns
1 ns
1 ns
MHz
(1) These parameters are ensured by design. The limits are based on statistical analysis of the device over PVT (process, voltage,
temperature) ranges.
(2) C_L includes probe and fixture capacitance.
(3) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50 Ω, t_r ≤ 1 ns, t_f ≤ 1 ns (10%-90%).
(4) All typicals are given for: V_CC = 3.3 V and T_A = 25°C.
(5) t_SKD1, |t_PHLD − t_PLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(6) t_SKD2 is the Differential Channel to Channel Skew of any event on the same device.
(7) t_SKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same V_CC and within 5°C of each other within the operating temperature range.
(8) t_SKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. t_SKD4 is defined as |Max − Min|
differential propagation delay.
(9) f_MAX generator input conditions: t_r = t_f < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%,
V_OD > 250 mV, all channels switching.
Copyright © 2000–2016, Texas Instruments Incorporated
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