DS90LV027A_16 Datasheet, PDF (4/21 Pages) Texas Instruments – LVDS Dual High Speed Differential Driver

DS90LV027A
SNLS026D – MARCH 2000 – REVISED JUNE 2016
6 Specifications
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6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
Supply voltage, V_CC
Input voltage, DI
Output voltage, DO±
Maximum package power dissipation at 25°C
Lead temperature range, soldering (4 s)
Storage temperature, T_stg
D package
Derate D package
MIN
MAX
UNIT
–0.3
4
V
–0.3
3.6
V
–0.3
3.9
V
1190
mW
9.5 mW/°C
above 25°C
°C
260
°C
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾
EIAJ, 0 Ω, 200 pF
IEC direct, 330 Ω, 150 pF
VALUE
±8000
±1000
±1000
±4000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V_CC
Supply voltage
T_A
Operating free-air temperature
MIN
NOM
MAX UNIT
3
3.3
3.6
V
–40
25
85
°C
6.4 Thermal Information
THERMAL METRIC⁽¹⁾
DS90LV027A
D (SOIC)
UNIT
R_θJA
Junction-to-ambient thermal resistance
Low-K thermal resistance⁽²⁾
High-K thermal resistance⁽²⁾
8 PINS
212
112
°C/W
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
69.1
°C/W
47.7
°C/W
15.2
°C/W
47.2
°C/W
—
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages.
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