DS90LV027A_16 Datasheet, PDF (10/21 Pages) Texas Instruments – LVDS Dual High Speed Differential Driver

DS90LV027A
SNLS026D – MARCH 2000 – REVISED JUNE 2016
8 Detailed Description
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8.1 Overview
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 19. This configuration provides a clean signaling environment for the fast edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media
is in the range of 100 Ω. A termination resistor of 100 Ω (selected to match the media), and is placed as close to
the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into
a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver
configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as
well as ground shifting, noise margin limits, and total termination loading must be considered. The DS90LV027A
differential line driver is a balanced current source design. A current mode driver, generally speaking has a high
output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand
supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce
a logic state and in the other direction to produce the other logic state. The output current is typically 3.1 mA, a
minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode driver requires (as discussed above) that a
resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 19. AC or
unterminated configurations are not allowed. The 3.1-mA loop current develops a differential voltage of 310 mV
across the 100-Ω termination resistor which the receiver detects with a 250-mV minimum differential noise
margin, (driven signal minus receiver threshold (250 mV – 100 mV = 150 mV). The signal is centered around 1.2
V (Driver Offset, VOS) with respect to ground as shown in Figure 18.
NOTE
The steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD)
and is typically 620 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case from 20 MHz to 50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires >80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
8.2 Functional Block Diagrams
DI 1
D
DO+ 1
DO- 1
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DI 2
D
DO+ 2
DO- 2
Copyright © 2016, Texas Instruments Incorporated
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