DRV8850 Datasheet, PDF (5/22 Pages) Texas Instruments – Low-Voltage H-Bridge IC With LDO Voltage Regulator

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DRV8850
SLVSCC0A – NOVEMBER 2013 – REVISED JANUARY 2014
Absolute Maximum Ratings⁽¹⁾⁽²⁾
over operating free-air temperature range (unless otherwise noted)
MIN TYP
MAX UNIT
VCC
Power supply voltage range
–0.3
7
V
VCP
Charge pump
–0.3
VCC + 7
LDOEN, IN1H, IN1L, IN2H, Digital pin voltage range
IN2L, nSLEEP
–0.5
7
OUT1, OUT2, SR, LDOUT, Other pins
LDOFB, VPROPI
–0.3
7
OUT1, OUT2
Peak motor drive output current
Internally Limited
A
LDOOUT
LDO output current
Internally Limited
T_J
T_STG
Operating junction temperature range
Storage temperature range
–40
150
°C
–60
150
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V_CC
I_OUT
I_OUT
f_PWM
V_IN
T_A
Device power supply voltage range
H-bridge continuous output current⁽¹⁾
H-bridge peak output current ⁽¹⁾
Externally applied PWM frequency
Logic level input voltage
Ambient temperature
(1) Power dissipation and thermal limits must be observed
MIN
NOM
MAX UNIT
2.0
5.5
V
0
5
A
0
8
A
0
50
kHz
0
V_CC
V
–40
85
°C
Thermal Information
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
THERMAL METRIC⁽¹⁾
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
DRV8850
PWP
RGY
24 PINS
24 PINS
43.8
39.1
24.6
41.1
22.7
15.0
0.7
0.6
22.5
14.9
4.1
3.2
UNIT
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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