BQ2970 Datasheet, PDF (5/31 Pages) Texas Instruments – Cost-Effective Voltage and Current Protection Integrated Circuit

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bq2970, bq2971, bq2972, bq2973
SLUSBU9C – MARCH 2014 – REVISED MARCH 2016
7 Specifications
7.1 Absolute Maximum Ratings⁽¹⁾
MIN
MAX
UNIT
Input voltage: BAT
Supply control and input
V– pin(pack–)
–0.3
12
V
BAT – 28 BAT + 0.3
V
DOUT (Discharge FET Output), GDSG (Discharge FET Gate Drive)
VSS – 0.3 BAT + 0.3
V
FET drive and protection COUT (Charge FET Output), GCHG (Charge FET Gate Drive)
BAT – 28 BAT + 0.3
V
Operating temperature: T_FUNC
Storage temperature, T_stg
–40
85
°C
–55
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
V_ESD ⁽¹⁾
Electrostatic
Discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽²⁾
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins ⁽³⁾
VALUE
±2000
±500
UNIT
V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 1000 V
may have higher performance.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V
may have higher performance.
7.3 Recommended Operating Conditions⁽¹⁾
MIN
MAX
UNIT
Supply control and
input
Positive input voltage: BAT
Negative input voltage: V–
–0.3
8
V
BAT – 25
BAT
V
FET drive and
protection
Discharge FET control: DOUT
Charge FET control: COUT
VSS
BAT
V
BAT – 25
BAT
V
Temperature Ratings
Operating temperature: T_Amb
Storage temperature: T_S
Lead temperature (soldering 10 s)
Thermal resistance junction to ambient, θ_JA(1)
–40
85
°C
–55
150
°C
300
°C
250
°C/W
(1) For more information about traditional and new thermal metrics, see the IC package Thermal Metrics application report, SPRA953.
7.4 Thermal Information
THERMAL METRIC⁽¹⁾
R_{θJA, High K}
R_θJC(top)
R_θJB
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
bq297xx
DSE (WSON)
12 PINS
190.5
94.9
149.3
UNIT
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
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