BQ2970 Datasheet, PDF (13/31 Pages) Texas Instruments – Cost-Effective Voltage and Current Protection Integrated Circuit

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SLUSBU9C – MARCH 2014 – REVISED MARCH 2016
8.2 Test Circuits
The following tests are referenced as follows: The COUT and DOUT outputs are “H,” which are higher than the
threshold voltage of the external logic level FETs and regarded as ON state. Conversely, “L” is less than the turn
ON threshold for external NMOS FETs and regarded as OFF state. The COUT pin is with respect to V–, and the
DOUT pin is with respect to VSS.
1. Overcharge detection voltage and overcharge release voltage (Test Circuit 1):
The overcharge detection voltage (V_OVP) is measured between the BAT and VSS pins, respectively. Once V1
is increased, the over-detection is triggered, and the delay timer expires, COUT transitions from a high to low
state and then reduces the V1 voltage to check for the overcharge hysteresis parameter (V_OVP-Hys). This delta
voltage between overcharge detection voltages (V_OVP) and the overcharge release occurs when the CHG
FET drive output goes from low to high.
2. Over-discharge detection voltage and over-discharge release voltage (Test Circuit 2):
Over-discharge detection (V_UVP) is defined as the voltage between BAT and VSS at which the DSG drive
output goes from high to low by reducing the V1 voltage. V1 is set to 3.5 V and gradually reduced while V2 is
set to 0 V. The over-discharge release voltage is defined as the voltage between BAT and VSS at which the
DOUT drive output transition from low to high when V1 voltage is gradually increased from a V_UVP condition.
The overcharge hysteresis voltage is defined as the delta voltage between V_UVP and the instance at which
the DOUT output drive goes from low to high.
3. Discharge overcurrent detection voltage (Test Circuit 2):
The discharge overcurrent detection voltage (V_OCD) is measured between V– and VSS pins and triggered
when the V2 voltage is increased above V_OCD threshold with respect to VSS. This delta voltage once
satisfied will trigger an internal timer t_OCDD before the DOUT output drive transitions from high to low.
4. Load short circuit detection voltage (Test Circuit 2):
Load short-circuit detection voltage (V_SCC) is measured between V– and VSS pins and triggered when the V2
voltage is increased above V_SCC threshold with respect to VSS within 10 µs. This delta voltage, once
satisfied, triggers an internal timer t_SCCD before the DOUT output drive transitions from high to low.
5. Charge overcurrent detection voltage (Test Circuit 2):
The charge overcurrent detection voltage (V_OCC) is measured between VSS and V– pins and triggered when
the V2 voltage is increased above V_OCC threshold with respect to V–. This delta voltage, once satisfied, l
triggers an internal timer t_OCCD before the COUT output drive transitions from high to low.
6. Operating current consumption (Test Circuit 2):
The operating current consumption I_BNORMAL is the current measured going into the BAT pin under the
following conditions: V1 = 3.9 V and V2 = 0 V.
7. Power down current consumption (Test Circuit 2):
The operating current consumption I_{Power_down} is the current measured going into the BAT pin under the
following conditions: V1 = 1.5 V and V2 = 1.5 V.
8. Resistance between V– and BAT pin (Test Circuit 3):
Measure the resistance (R_{V_D}) between V– and BAT pins by setting the following conditions: V1 = 1.8 V and
V2 = 0 V.
9. Current sink between V– and VSS (Test Circuit 3):
Measure the current sink I_V–S between V– and VSS pins by setting the following condition: V1 = 4 V.
10. COUT current source when activated High (Test Circuit 4):
Measure I_COUT current source on the COUT pin by setting the following conditions: V1 = 3.9 V, V2 = 0 V and
V3 = 3.4 V.
11. COUT current sink when activated Low (Test Circuit 4):
Measure I_COUT current sink on COUT pin by setting the following conditions: V1 = 4.5 V, V2 = 0 V and V3 =
0.5 V.
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