74ACT11874 Datasheet, PDF (5/7 Pages) Texas Instruments – DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

ą
From Output
Under Test
CL = 50 pF
(see Note A)
74ACT11874
DUAL 4ĆBIT DĆTYPE EDGEĆTRIGGERED FLIPĆFLOPS
WITH 3ĆSTATE OUTPUTS
SCAS212 − D3447, MARCH 1990 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
500 Ω
500 Ω
2 × VCC
S1
Open
GND
TEST
tPLH /tPHL
tPLZ /tPZL
tPHZ /tPZH
S1
Open
2 × VCC
GND
LOAD CIRCUIT
Input
tw
3V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
Timing Input
(see Note B)
tsu
3V
1.5 V
0V
th
3V
Data Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
Input
(see Note B)
1.5 V
3V
1.5 V
0V
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
50% VCC
50% VCC
tPHL
VOH
50% VCC
VOL
tPLH
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
tPZL
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
tPZH
1.5 V
1.5 V
tPLZ
50% VCC
tPHZ
20% VCC
50% VCC
80% VCC
VOLTAGE WAVEFORMS
3V
0V
[ VCC
VOL
VOH
[0V
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
2−5