74ACT11874 Datasheet, PDF (4/7 Pages) Texas Instruments – DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

74ACT11874
DUAL 4ĆBIT DĆTYPE EDGEĆTRIGGERED FLIPĆFLOPS
WITH 3ĆSTATE OUTPUTS
SCAS212 − D3447, MARCH 1990 − REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range,
V_CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN TYP MAX
MIN MAX UNIT
fclock Clock frequency
tw
Pulse duration
CLR low
CLK high or low
0
125
0 125 MHz
2
4
ns
2
4
tsu _{Setup time before CLK↑}
Data
CLR low
1
5
ns
2
2
th
Hold time after CLK↑
Data
2
1
ns
switching characteristics over recommended operating free-air temperature range,
V_CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
MIN TYP MAX
MAX UNIT
fmax
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
CLK
CLR
OE
OE
Any Q
Any Q
Any Q
Any Q
125
7.5
8.1
8.8
6.4
8.6
6.9
6.8
125
MHz
3.7 9.4
ns
4.1 10.6
3.5 11.8 ns
1.6 7.4
ns
2.4 9.5
5.4 9.4
ns
4.9 9.1
operating characteristics, V_CC = 5 V, T_A = 25°C
PARAMETER
Cpd
Power dissipation capacitance
Outputs enabled
Outputs disabled
TEST CONDITIONS
CL = 50 pF, f = 1 MHz
TYP UNIT
76
pF
64
2−4
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