LM3S9D92_16 Datasheet, PDF (481/1412 Pages) Texas Instruments – Stellaris LM3S9D92 Microcontroller

Stellaris^® LM3S9D92 Microcontroller
9.4.2.5
communication devices (including USB2 devices), and some FPGA configurations (FIFO through
block RAM). This sub-mode provides the data side of the normal Host-Bus interface, but is
paced by the FIFO control signals. It is important to consider that the XFIFO FULL/EMPTY
control signals may stall the interface and could have an impact on blocking read latency from
the processor or μDMA.
The WORD bit in the EPIHBnCFG2 register can be set to use memory more efficiently. By default,
the EPI controller uses data bits [7:0] for Host-Bus 8 accesses or bits [15:0] for Host-Bus 16 accesses.
When the WORD bit is set, the EPI controller can automatically route bytes of data onto the correct
byte lanes such that bytes or words of data can be transferred on the correct byte or half-word bits
on the entire bus. For example, the most significant byte of data will be transferred on bits [31:28]
in host-bus 8 mode and the most significant word of data will be transferred on bits [31:16] of
Host-Bus 16 mode. In addition, for the three modes above (1, 2, 4) that the Host-Bus 16 mode
supports, byte select signals can be optionally implemented by setting the BSEL bit in the
EPIHB16CFG register.
Note: Byte accesses should not be attempted if the BSEL bit has not been enabled in Host-Bus
16 Mode.
See “External Peripheral Interface (EPI)” on page 1326 for timing details for the Host-Bus mode.
Bus Operation
Bus operation is the same in Host-Bus 8 and Host-Bus 16 modes and is asynchronous. Timing
diagrams show both ALE and CSn operation, but only one signal or the other is used in all modes
except for ALE with dual chip selects mode (CSCFG field is 0x3 in the EPIHBnCFG2 register).
Address and data on write cycles are held after the CSn signal is deasserted. The optional HB16
byte select signals have the same timing as the address signals. If wait states are required in the
bus access, they can be inserted during the data phase of the access using the WRWS and RDWS
bits in the EPIHBnCFG2 register. Each wait state adds 2 EPI clock cycles to the duration of the
WRn or RDn strobe. During idle cycles, the address and muxed address data signals maintain the
state of the last cycle.
Figure 9-6 on page 481 shows a basic Host-Bus read cycle. Figure 9-7 on page 482 shows a basic
Host-Bus write cycle. Both of these figures show address and data signals in the non-multiplexed
mode (MODE field ix 0x1 in the EPIHBnCFG register).
Figure 9-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
BSEL0n/
BSEL1n^a
Address
Data
a _{BSEL0n and BSEL1n are available in Host-Bus 16 mode only.}
Data
July 03, 2014
481
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