TLC34075A Datasheet, PDF (48/53 Pages) Texas Instruments – Video Interface Palette Data Manual

Appendix C
SCLK Frequency < VCLK Frequency
The VCLK and SCLK outputs generated by the TLC34075A are both free-running clocks. The video control
signals (i.e., HSYNC, VSYNC, and BLANK) are normally generated from VCLK, and a fixed relationship
between the video control signals and VCLK can therefore be expected. The TLC34075A samples and
latches the BLANK input on the falling edge of VCLK. It then looks at the LOAD signal to determine when
to disable or enable SCLK at its output terminal. The decision is deterministic when the SCLK frequency
is greater than or equal to the VCLK frequency. However, when the SCLK frequency is less than the VCLK
frequency, the appearance of the SCLK waveform at its output terminal when BLANK is sampled low on the
VCLK falling edge can vary (see Figures C –1 and C – 2).
To avoid this variation in the SCLK output waveform, the SCLK and VCLK frequencies should be chosen
so that HTOTAL is evenly divisible by the ratio of (VCLK frequency:SCLK frequency); that is,
ȧȱ ^{ȳȧ + remainder of}
HTOTAL
0.
VCLK frequency
Ȳ^{ǒ Ǔ}ȴ SCLK frequency
For example, if HTOTAL is even, VCLK frequency = DOTCLK frequency/8, and SCLK frequency =
DOTCLK frequency/16, then the formula above is satisfied. NOTE: When HTOTAL starts at zero (as in the
TMS340x0 GSP), then the formula becomes
ȱ ₎ ȳ _{(HTOTAL 1)}
ȧ ȧ ^{+ remainder of}
0.
VCLK frequency
Ȳ^{ǒ Ǔ}ȴ SCLK frequency
VCLK
BLANK
LOAD
(Internal Signal
for Data Latch)
SCLK at
Output Terminal
Figure C –1. VCLK and SCLK Phase Relationship (Case 1)
C-1