TLC34075A Datasheet, PDF (27/53 Pages) Texas Instruments – Video Interface Palette Data Manual

The relationship between R_SET and the full-scale output current IOG is:
R_SET (Ω) = K1 × V_REF (V) / IOG (mA)
The full-scale output current on IOR and IOB for a given R_SET is:
IOR, IOB (mA) = K2 × V_REF (V) / R_SET (Ω)
where K1 and K2 are defined as:
PEDESTAL
7.5-IRE
0-IRE
IOG
8-BIT OUTPUT 6-BIT OUTPUT
K1 = 11,294
K1 = 11,206
K1 = 10,684
K1 = 10,600
IOR, IOB
8-BIT OUTPUT 6-BIT OUTPUT
K2 = 8,067
K2 = 7,979
K2 = 7,462
K2 = 7,374
2.8 HSYNC, VSYNC, and BLANK
For the normal modes, HSYNC and VSYNC are active-low pulses, and they are passed through
true/complement gates to the HSYNCOUT and VSYNCOUT outputs. The output polarities of HSYNCOUT
and VSYNCOUT can be programmed through the general control register. However, for the VGA
pass-through mode, the polarities needed for monitors are already provided at the feature connector from
which HSYNC and VSYNC are sourced, so the TLC34075A just passes HSYNC and VSYNC through to
HSYNCOUT and VSYNCOUT without polarity change. As described in Section 2.3 and Figures 2– 2
through 2– 5, the BLANK, HSYNC, and VSYNC inputs are sampled and latched on the falling edge of VCLK
in the normal modes, and they are latched on the rising edge of the CLK0 input in the VGA pass-through
mode. Refer to Figure 3– 2 for the detailed timing.
The HSYNC and VSYNC inputs are used for both the VGA pass-through and normal modes. If the
application uses both VGA pass-through and normal modes, an external multiplexer is needed to select
HSYNC and VSYNC between VGA pass-through mode and normal mode. The MUXOUT signal is designed
for this purpose (see Sections 2.10 and 2.11).
The HSYNC, VSYNC, and BLANK signals have internal pipeline delays to align the data at the outputs. Due
to the sample and latch timing delay, it is possible to have active SCLK pulses after the BLANK input
becomes active. The relationship between VCLK and SCLK and the internal VCLK sample and latch delay
need to be carefully reviewed and programmed. See Section 2.3 and Figures 2–2 and 2–3 for more details.
As shown in Figure 2– 6 for the IOG DAC output, active HSYNC and VSYNC signals turn off the sync current
source (after the pipeline delay) independent of the BLANK signal level. In real applications, HSYNC and
VSYNC should only be active (low) when BLANK is active (low).
To alter the polarity of the HSYNCOUT and VSYNCOUT outputs in the normal modes, the MPU must set
or clear the corresponding bits in the general control register (see Section 2.11.1). Again, these two bits
affect only the normal modes, not the VGA pass-through mode. These bits default to 1.
2.9 Split Shift Register Transfer VRAMs and Special Nibble Mode
2.9.1 Split Shift Register Transfer VRAMs
The TLC34075A directly supports split shift register transfer (SSRT) VRAMs. In order to allow the VRAMs
to perform a split shift register transfer, an extra SCLK cycle must be inserted during the blank sequence.
This is initiated when the SSRT enable bit (bit 2 in the general control register) is set to 1, the SNM bit (bit 3
in the general control register) is reset to 0 (see Section 2.11), and a rising edge on the SFLAG/NFLAG input
pin is detected. An SCLK pulse is generated within 20 ns of the rising edge of the SFLAG/NFLAG signal.
A minimum 15-ns high logic level duration is provided to satisfy all of the – 15 VRAM requirements. By
controlling the SFLAG/NFLAG rise time, the delay time from the rising edge of the VRAM TRG signal to
SCLK can be satisfied. The relationship between the SCLK, SFLAG/NFLAG, and BLANK signals is as
follows:
2-14