TLC34075A Datasheet, PDF (17/53 Pages) Texas Instruments – Video Interface Palette Data Manual

Table 2– 4. Output Clock Selection Register Format
BITS ^†
5
4
3
2
1
0
FUNCTION ^‡
0
0
0
X
X
X VCLK frequency = DOTCLK frequency
0
0
1
X
X
X VCLK frequency = DOTCLK frequency/2
0
1
0
X
X
X VCLK frequency = DOTCLK frequency/4
0
1
1
X
X
X VCLK frequency = DOTCLK frequency/8
1
0
0
X
X
X VCLK frequency = DOTCLK frequency/16
1
0
1
X
X
X VCLK frequency = DOTCLK frequency/32
1
1
X
X
X
X VCLK output held at logic high level (default condition)§
X
X
X
0
0
0 SCLK frequency = DOTCLK frequency
X
X
X
0
0
1 SCLK frequency = DOTCLK frequency/2
X
X
X
0
1
0 SCLK frequency = DOTCLK frequency/4
X
X
X
0
1
1 SCLK frequency = DOTCLK frequency/8
X
X
X
1
0
0 SCLK frequency = DOTCLK frequency/16
X
X
X
1
0
1 SCLK frequency = DOTCLK frequency/32
X
X
X
1
1
X SCLK output held at logic level low (default condition)§
† _{Register bits 6 and 7 are don’t care bits.}
‡ _{When the clock selection is altered, a minimum 30-ns delay is incurred before the new clocks are}
stabilized and running.
§ _{These lines indicate the power-up conditions required to support the VGA pass-through mode.}
Table 2– 5. VCLK/SCLK Divide Ratio Selection
(Output Clock Selection Register Value in Hex)
SCLK
VCLK
BITS
2. . . 0¶
000 001 010 011 100 101
divide DOTCLK by
BITS
5. . .3¶
divide
DOTCLK
1
2
4
8
16
32
000
by ₁
00
01
02
03
04
05
001
2
08
09
0A
0B
0C
0D
010
4
10
11
12
13
14
15
011
8
18
19
1A
1B
1C
1D
100
16
20
21
22
23
24
25
101
32
¶ _{Output clock selection register bits}
28
29
2A
2B
2C
2D
2.3.1 SCLK
The TLC34075A latches data on the rising edge of the LOAD signal (LOAD is the same as SCLK but is not
disabled while the BLANK signal is active). Therefore, SCLK must be set as a function of the pixel bus width
and the number of bit planes. The SCLK frequency can be selected to be the same as the dot clock
frequency or 1/2, 1/4, 1/8, 1/16, or 1/32 of the dot clock frequency. If SCLK is not used, the output is switched
off and held low to protect against VRAM lock-up due to invalid SCLK frequencies. SCLK is also held low
during the BLANK signal active period. The control timing has been designed to bring the first pixel data
ready from the VRAM when BLANK is disabled and ready for the display. When split shift register transfer
operation is used, SCLK is taken care of by working with SSRT input (see Section 2.9).
Refer to Figure 2– 2 for the following timing explanation.
2-4