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TLC34075A Datasheet, PDF (37/53 Pages) Texas Instruments – Video Interface Palette Data Manual
3.5 Timing Requirements (see Note 5)
PARAMETER
TLC34075A TLC34075A
-66
-85
MIN MAX MIN MAX
TLC34075A
-110
MIN MAX
TLC34075A
-135
MIN MAX
UNIT
DOTCLK frequency
66
85
110
135 MHz
CLK0 frequency for VGA
pass-through mode (see Note 6)
66
85
85
85 MHz
TTL 15.2
11.8
9.1
tcyc Clock cycle time
ECL 15.2
11.8
9.1
7.4
ns
7.4
tsu1
Setup time, RS<0:3>
valid before RD or WR ↓
10
10
10
10
ns
th1
Hold time, RS<0:3> valid
after RD or WR ↓
10
10
10
10
ns
tsu2
Setup time, D<0:7> valid
before WR ↑
35
35
35
35
ns
th2
Hold time, D<0:7> valid
after WR ↑
0
0
0
0
ns
Setup time, VGA<0:7> and
tsu3 HSYNC, VSYNC, and
2
2
2
VGABLANK valid before CLK0 ↑
2
ns
Hold time, VGA<0:7> and
th3 HSYNC, VSYNC, and
2
2
2
VGABLANK valid after CLK0 ↑
2
ns
tsu4
Setup time, P<0:31> valid before
SCLK ↑
2
2
2
0
ns
th4
Hold time, P<0:31> valid after
SCLK ↑
5
5
5
5
ns
Setup time, HSYNC, VSYNC,
tsu5 and BLANK valid before VCLK ↓
5
5
5
5
ns
th5
Hold time, HSYNC, VSYNC, and
BLANK valid after VCLK ↓
2
2
2
2
ns
tw1 Pulse duration, RD or WR low
50
tw2 Pulse duration, RD or WR high
30
TTL
4.5
tw3
Pulse duration, clock high
ECL
5.5
50
50
30
30
4
3.5
4
3.5
50
ns
30
ns
3
3
ns
TTL
4.5
tw4 Pulse duration, clock low
ECL
5.5
4
3.5
4
3.5
3
ns
3
tw5
Pulse duration, SFLAG/NFLAG
high (see Note 7)
30
30
30
30
ns
NOTES: 5. TTL input signals are 0 to 3 V with less than 3 ns rise/fall time between the 10% and 90% levels unless
otherwise specified. ECL input signals are VDD –1.8 V to VDD – 0.8 V with less than 2 ns rise/fall time between
the 20% and 80% levels. For input and output signals, timing reference points are at the 10% and 90% signal
levels. Analog output loads are less than 10 pF. D<0:7> output loads are less than 50 pF. All other output loads
are less than 50 pF unless otherwise specified.
6. In VGA mode, CLK0 minimum pulse duration for clock low should be greater than 4.8 ns.
7. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.9.1
for details.
3-4