TM4C123BH6PGE Datasheet, PDF (478/1333 Pages) Texas Instruments – Tiva TM4C123BH6PGE Microcontroller

System Control
Register 137: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC2 is the clock configuration register for
running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Important: This register is provided for legacy software support only.
The peripheral-specific Deep Sleep Mode Clock Gating Control registers (such as
DCGCDMA) should be used to reset specific peripherals. A write to this legacy register
also writes the corresponding bit in the peripheral-specific register. Any bits that are
changed by writing to this register can be read back correctly with a read of this register.
Software must use the peripheral-specific registers to support modules that are not
present in the legacy registers. If software uses a peripheral-specific register to write a
legacy peripheral (such as the μDMA), the write causes proper operation, but the value
of that bit is not reflected in this register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
reserved
UDMA
Type RO
RO
RO
RO
Reset
0
0
0
0
11
10
reserved
RO
RO
0
0
9
8
7
6
5
4
3
2
1
0
GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:14
13
Name
reserved
UDMA
Type
RO
RO
Reset
0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
478
June 12, 2014
Texas Instruments-Production Data