LM3S5791_16 Datasheet, PDF (476/1336 Pages) Texas Instruments – Stellaris LM3S5791 Microcontroller

External Peripheral Interface (EPI)
– Implementing a very wide ganged PWM/PCM with fixed frequency for driving actuators, LEDs,
etc.
– Implementing SDIO 4-bit mode where commands are driven or captured on 6 pins with fixed
timing, fed by the µDMA.
■ General custom interfaces of any speed.
The configuration allows for choice of an output clock (free-running or gated), a framing signal (with
frame size), a ready input (to stretch transactions), a read and write strobe, an address (of varying
sizes), and data (of varying sizes). Additionally, provisions are made for separating data and address
phases.
The interface has the following optional features:
■ Use of the EPI clock output is controlled by the CLKPIN bit in the EPIGPCFG register. Unclocked
uses include general-purpose I/O and asynchronous interfaces (optionally using RD and WR
strobes). Clocked interfaces allow for higher speeds and are much easier to connect to FPGAs
and CPLDs (which usually include input clocks).
■ EPI clock, if used, may be free running or gated depending on the CLKGATE bit in the EPIGPCFG
register. A free-running EPI clock requires another method for determining when data is live,
such as the frame pin or RD/WR strobes. A gated clock approach uses a setup-time model in
which the EPI clock controls when transactions are starting and stopping. The gated clock is
held high until a new transaction is started and goes high at the end of the cycle where
RD/WR/FRAME and address (and data if write) are emitted.
■ Use of the ready input (iRDY) from the external device is controlled by the RDYEN bit in the
EPIGPCFG register. The iRDY signal uses EPI0S27 and may only be used with a free-running
clock. iRDY gates transactions, no matter what state they are in. When iRDY is deasserted, the
transaction is held off from completing.
■ Use of the frame output (FRAME) is controlled by the FRMPIN bit in the EPIGPCFG register.
The frame pin may be used whether the clock is output or not, and whether the clock is free
running or not. It may also be used along with the iRDY signal. The frame may be a pulse (one
clock) or may be 50/50 split across the frame size (controlled by the FRM50 bit in the EPIGPCFG
register). The frame count (the size of the frame as specified by the FRMCNT field in the
EPIGPCFG register) may be between 1 and 15 clocks for pulsed and between 2 and 30 clocks
for 50/50. The frame pin counts transactions and not clocks; a transaction is any clock where
the RD or WR strobe is high (if used). So, if the FRMCNT bit is set, then the frame pin pulses
every other transaction; if 2-cycle reads and writes are used, it pulses every other address phase.
FRM50 must be used with this in mind as it may hold state for many clocks waiting for the next
transaction.
■ Use of the RD and WR outputs is controlled by the RW bit in the EPIGPCFG register. For interfaces
where the direction is known (in advance, related to frame size, or other means), these strobes
are not needed. For most other interfaces, RD and WR are used so the external peripheral knows
what transaction is taking place, and if any transaction is taking place.
■ Separation of address/request and data phases may be used on writes using the WR2CYC bit in
the EPIGPCFG register. This configuration allows the external peripheral extra time to act.
Address and data phases must be separated on reads, and the RD2CYC bit in the EPIGPCFG
register must be set. When configured to use an address as specified by the ASIZE field in the
EPIGPCFG register, the address is emitted on the with the RD strobe (first cycle) and data is
476
July 03, 2014
Texas Instruments-Production Data