ADC08B3000 Datasheet, PDF (47/57 Pages) National Semiconductor (TI) – High Performance, Low Power, 8-Bit, 3 GSPS A/D Converter with 4K Buffer

ADC08B3000
www.ti.com
SNAS331M – JUNE 2006 – REVISED APRIL 2013
The internal power-on calibration circuitry comes up in an unknown logic state. If the input clock is not running at
power up and the power on calibration circuitry is active, it will hold the analog circuitry in power down and the
power consumption will typically be less than 25 mW. The power consumption will be normal after the clock
starts.
On-Command Calibration
To initiate an on-command calibration, bring the CAL pin high for a minimum of 80 input clock cycles after it has
been low for a minimum of 80 input clock cycles. Holding the CAL pin high upon power up will prevent execution
of power-on calibration until the CAL pin is low for a minimum of 80 input clock cycles, then brought high for a
minimum of another 80 input clock cycles. The calibration cycle will begin 80 input clock cycles after the CAL pin
is thus brought high. The CalRun signal should be monitored to determine when the calibration cycle has
completed.
The minimum t_{CAL_L}and t_{CAL_H} input clock cycle sequence is required to ensure that random noise does not
cause a calibration to begin when it is not desired. As mentioned in Calibration, for best performance a
calibration should be performed 20 seconds or more after power up because and repeated when the operating
temperature changes significantly relative to the specific system design performance requirements. The
suggestion for performing an on-command calibration 20 seconds or more after application of power is because
dynamic performance changes with a large change in die temperature and that temperature is nearly stable
about 20 seconds after application of power. Dynamic performance changes slightly with increasing junction
temperature and can be easily corrected by performing an on-command calibration.
Both the ADC and the input termination resistor are calibrated during a power-on calibration cycle. By default, on-
command calibration includes calibration of the input termination resistor and the ADC. However, since the input
termination resistor changes only slightly with temperature, the user has the option to disable the input
termination resistor trim, once trimmed at power up. The Resistor Trim Disable can be programmed in the
Configuration Register when in the Extended Control mode.
Calibration Delay
The CalDly input (pin 127) is used to select one of two delay times after the application of power to the start of
calibration, as described in Calibration. The calibration delay values allow the power supply to come up and
stabilize before calibration takes place. With no delay or insufficient delay, calibration might begin before the
power supply is stabilized at its operating value and result in non-optimal calibration coefficients. If the PD pin is
high upon power-up, the calibration delay counter will be disabled until the PD pin is brought low. Therefore,
holding the PD pin high during power up will further delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling time of the power supply.
Note that the calibration delay selection is not possible in the Extended Control mode and the short delay time is
used.
Input Termination Resistor Trim
The calibration algorithm also trims the input signal termination resistor. This is essential for proper operation of
the device. Once trimmed upon power-up, however, it is not essential for proper operation of the device. Once
trimmed, however, it is not necessary to trim the resistor at each subsequent calibration. The RTD bit in the
Configuration Register allows the user to disable input resistor trim. It is required that this RTD bit be set to 1b if
the Clock Phase Adjust feature is used.
Output Edge Synchronization
OutEdge is an input available to help latch the converter output data into external circuitry. This pin may make
data capture easier, especially when output clock and data trace lengths are not matched. This pin allows the
user to shift the phase of the Data Ready pins (DRDY1 and DRDY2) with respect to the data outputs. See
Double Data Rate.
Power Down Feature
The Power Down pin (PD) allows the ADC08B3000 to be powered down while the capture buffer is still active so
that it may be read. See Power Down for details on the power down feature.
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