ADC08B3000 Datasheet, PDF (23/57 Pages) National Semiconductor (TI) – High Performance, Low Power, 8-Bit, 3 GSPS A/D Converter with 4K Buffer

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RESET
WEN
Write CLK
(Internal)
WENsync
FF
EF
REN
D1 <7:0>
ADC08B3000
SNAS331M – JUNE 2006 – REVISED APRIL 2013
t_{HWEN (min)}
t_DWS2
FF asserted with 512^th data bit written into Capture Buffer
if BSIZE<1:0> = 00b
3T_{WRITE CLK}
DRDY
A. t_HWEN: WEN is internally latched on the 4th rising edge of the internal write clock (see Figure 16)
Figure 16. Capture Buffer End of WRITE Phase (ASW = 1b)
RESET
WEN
Write CLK
(Internal)
WENsync
FF
EF
REN
WEN deassertion
stops data storage
3T_{WRITE CLK}
t_DWS1
FF asserted with 512^th data bit written into Capture Buffer
if BSIZE<1:0> = 00b
7T_{WRITE CLK}
D1 <7:0>
DRDY
Figure 17. Capture Buffer End of WRITE Phase (ASW = 0b)
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