ADC08B3000 Datasheet, PDF (12/57 Pages) National Semiconductor (TI) – High Performance, Low Power, 8-Bit, 3 GSPS A/D Converter with 4K Buffer

ADC08B3000
SNAS331M – JUNE 2006 – REVISED APRIL 2013
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Converter Electrical Characteristics⁽¹⁾⁽²⁾ (continued)
The following specifications apply after calibration for V_A = V_DR = 1.9V, V_IN FSR (a.c. coupled) = differential 810mV_P-P,
C_L = 10 pF, Differential a.c. coupled sine wave Input Clock, f_CLK = 1.5 GHz at 0.4V_P-P with 50% duty cycle, Duty Cycle
Stabilizer enabled, RCLK = 100 MHz, V_BG = Floating, Non-Extended Control Mode, SDR Mode, R_EXT = 3300Ω ±0.1%, Analog
Signal Source Impedance = 100Ω Differential, after calibration. Boldface limits apply for T_A = T_MIN to T_MAX. All other limits
T_A = 25°C, unless otherwise noted.
Parameter
Test Conditions
Typical ⁽³⁾
Limits ⁽³⁾
Units
(Limits)
LVCMOS INPUT CHARACTERISTICS
V_IH
Logic High Input Voltage
V_IL
Logic Low Input Voltage
I_IH
Logic High Input Current
ADCCLK_RST, PD, CAL
OutEdge, FSR, CalDly
All LVCMOS Inputs
ADCCLK_RST, CAL, PD,
CalDly
FSR/ECE
0.69 x V_A
0.79 x V_A
0.28 x V_A
V (min)
V (min)
V (max)
1
µA
30
µA
I_IL
Logic Low Input Current
C_IN
Input Capacitance⁽⁶⁾
LVCMOS OUTPUT CHARACTERISTICS
ADCCLK_RST, CAL, PD,
CalDly
1
µA
FSR/ECE
30
µA
Each input to ground
1.2
pF
V_OH
CMOS High level output
V_OL
CMOS Low level output
POWER SUPPLY CHARACTERISTICS
I_OH = -400uA
I_OH = 400uA
1.65
1.5
V (min)
0.15
0.3
V (max)
I_A
Analog Supply Current
Full Power Capture Mode
WEN = High,
REN =PD = Low
Power Down Mode
WEN = Low,
REN = PD = High
723
800
mA (max)
2.4
mA
I_DR
Output Driver Supply Current
Full Power Capture Mode
WEN = High,
REN =PD = Low
Power Down Mode
WEN = Low,
REN = PD = High
135
180
mA (max)
10.8
mA
P_D
Power Consumption
Full Power Capture Mode
WEN = High,
REN =PD = Low
Power Down Mode
WEN = Low,
REN = PD = High
1.6
1.9
W (max)
25
mW
PSRR1 D.C. Power Supply Rejection Ratio
Change in Offset Error with
change in V_A from 1.8V to 2.0V
70
dB
PSRR2 A.C. Power Supply Rejection Ratio
248 MHz, 100mV_P-P riding on
V_A
50
dB
(6) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated
from the die capacitances by lead and bond wire inductances.
12
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