ADC08B3000 Datasheet, PDF (13/57 Pages) National Semiconductor (TI) – High Performance, Low Power, 8-Bit, 3 GSPS A/D Converter with 4K Buffer

ADC08B3000
www.ti.com
SNAS331M – JUNE 2006 – REVISED APRIL 2013
Converter Electrical Characteristics⁽¹⁾⁽²⁾ (continued)
The following specifications apply after calibration for V_A = V_DR = 1.9V, V_IN FSR (a.c. coupled) = differential 810mV_P-P,
C_L = 10 pF, Differential a.c. coupled sine wave Input Clock, f_CLK = 1.5 GHz at 0.4V_P-P with 50% duty cycle, Duty Cycle
Stabilizer enabled, RCLK = 100 MHz, V_BG = Floating, Non-Extended Control Mode, SDR Mode, R_EXT = 3300Ω ±0.1%, Analog
Signal Source Impedance = 100Ω Differential, after calibration. Boldface limits apply for T_A = T_MIN to T_MAX. All other limits
T_A = 25°C, unless otherwise noted.
Parameter
Test Conditions
Typical ⁽³⁾
Limits ⁽³⁾
Units
(Limits)
AC ELECTRICAL CHARACTERISTICS - Sample Clock
f_CLK1
f_CLK2
t_CYC
t_LC
t_HC
t_AD
Maximum Input Clock Frequency
Minimum Input Clock Frequency
Input Clock Duty Cycle
Input Clock Low Time
Input Clock High Time
Sample (Aperture) Delay
Sample rate is 2x clock input
Sample rate is 2x clock input
500
500MHz ≤ Input clock frequency
≤ 1.5 GHz⁽⁷⁾
50
See ⁽⁸⁾
333
See ⁽⁸⁾
333
Input CLK transition to
Acquisition of Data
1.4
1.5
GHz (min)
MHz
20
% (min)
80
% (max)
133
ps (min)
133
ps (min)
ns
t_AJ
Aperture Jitter
AC ELECTRICAL CHARACTERISTICS - Capture Buffer Signals
0.55
ps rms
f_RCLK
Maximum Capture Buffer Read Clock Frequency
200
t_LHT
Low to High Transition Time
10% to 90%
250
t_HLT
High to Low Transition Time
10% to 90%
250
t_DWS1
Delay WENSYNC
Delay after 3 Write Clock
Cycles
7.0
MHz
ps
ps
ns
t_DWS2
t_HWEN
Delay WENSYNC
Minimum Hold Time WEN
Delay after FF assertion
-1.3
ns
Hold Time after WENSYNC
deassertion
-5.0
0
ns (min)
T_ASWEN Minimum Assertion Delay WEN
RCLK cycle delay after
deassertion of REN
0
1
RCLK
Cyc. (min)
t_DFF
Delay Full Flag
Delay after REN assertion,
RCLK = 100 MHz
7.3
ns
Delay after REN assertion,
RCLK = 200 MHz
5.0
ns
t_DEF1
Delay Empty Flag
Delay after last DRDY pulse,
RCLK = 200 MHz
0
ns
t_DEF2
t_DEF3
Delay Empty Flag
Delay Empty Flag
Delay after RESET
2.0
ns
Delay after WENSYNC
assertion
9.5
ns
t_SREN
Minimum Setup Time REN
Setup Time before rising edge
of RCLK
0.2
0.3
ns (min)
t_HREN
Minimum Hold Time REN
Hold Time after last DRDY
pulse or positive edge of
RESET
-5
0
ns (min)
t_DDRDY
Delay RCLK to DRDY
RCLK to DRDY Delay, RCLK =
100 MHz or 200 MHz
2.7
1.8
ns (min)
4.0
ns (max)
t_SKEW
Skew DRDY to Data
For SDR and
DDR 0º modes.
0
±200
ps (max)
t_SO
Setup Time Data Output
Data Output to DRDY
For DDR 90º mode
5
ns
t_HO
Hold Time Data Output
DRDY to Data Output
For DDR 90º mode
5
ns
(7) This parameter is ensured by design and/or characterization and is not tested in production.
(8) This parameter is ensured by design and is not tested in production.
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