TNETA1570 Datasheet, PDF (46/68 Pages) Texas Instruments – ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE

TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64ĆBIT PCIĆHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
PRINCIPLES OF OPERATION
reassembly time-out processing per VC
When the reassembly engine reaches the state to begin processing, the next received cell in the receive-cell
queue , it first checks the aging timer to see if a global time-out has occurred. If a global time-out has occurred,
a single-VC aging operation is performed before the next cell in queue is processed.
The reassembly-aging timer uses the receive VPI/VCI DMA pointer table to select a DMA channel for a
single-VC aging operation. The VPIs for aging are selected one at a time in consecutive order starting at zero,
providing one VPI/VCI combination the opportunity to be processed for each global time-out.
The single-VC operation starts with checking the enable bit for the next entry in the RX VPI/VCI DMA pointer
table. If the VPI is disabled, the aging opportunity is terminated. If the VPI is enabled, the base pointer and
VCI-incrementer value are used to form the base address of the receive DMA state entry to be processed.
For the aging opportunity to continue, the selected DMA entry must be active, not in the wait-on-EOP state, and
be in use for either AAL5- or PTI-based transparent packets. If this is true, the time-out-count value of the entry
is incremented and compared to the time-out value. If the reassembly time-out-count value is equal to the
time-out value for the VC, the TNETA1570 device implements EOP processing on the packet associated with
this RX DMA state table entry, including a write to the RX completion ring denoting that time-out has occurred.
terminating aging opportunity
At the termination of each aging opportunity, several control elements of the reassembly-aging timer are
updated.
D The VCI value is incremented by one. If this value exceeds the valid VCI range for the VPI which points to
the current RX VPI/VCI DMA pointer-table entry, or if the current RX VPI/VCI-DMA-pointer entry is not
enabled, the VPI index is incremented on the next aging opportunity.
D The RAT cycle-count timer is also incremented by one at the end of each aging opportunity. This counter
is compared to the RAT cycle-count register in the next aging opportunity. The VPI index is reset to zero
beginning a new timer pass through the RX VPI/VCI DMA pointer table when these values are equal.
If the VPI index reaches 4095, the VCI index exceeds the valid VCI range for the VPI, and the internal RAT
cycle-count-timer value is less than the RAT cycle-count register, aging opportunities are terminated
immediately and the reassembly-aging timer waits for the RAT reset to occur.
formula for time-out time period
The time to time-out a packet on a per VC basis is determined by the following formula:
Time-out time period = (1/PCI clock) × (global RAT timer-register value) × (RAT cycle-count register value) ×
(time-out value in word 7 of the RX DMA state table)
receive idle cells handling
If the received cell is an idle cell, (i.e., a cell with the ATM header set to a binary value of xxxx 0000 0000 0000
0000 0000 0000 xxx 1), the ATM header, including the VPI/VCI value, is written to the RX unknown register, an
interrupt is generated if enabled, and the unknown-protocols counter is increased.
cell interface
The TNETA1570 connects to the transmission logic through the cell interface. The cell interface is configured
as a PHY interface with the option to be configured as an ATM interface. The operation of this dual interface
requires the use of two external pins, ATMCLK and PHY/ATM.
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