TNETA1570 Datasheet, PDF (21/68 Pages) Texas Instruments – ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE

TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64ĆBIT PCIĆHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
PRINCIPLES OF OPERATION
segmentation overview (continued)
The last possibility for an active DMA channel is the start of a new packet. This is detected by the cleared ACT
status of the DMA channel. In this case, the packet-segmentation ring-base offset pointer and its index fields
of the DMA entry are used to acquire a new buffer address from the packet-segmentation ring for the virtual
channel. If the packet-segmentation-ring entry is owned by the TNETA1570, the pointer contained in the entry
is used to acquire a new segmentation buffer, the ACT bit of the DMA channel is set, and the
packet-segmentation-ring index is incremented. Packet segmentation for the DMA channel is terminated for this
cell opportunity if the packet-segmentation-ring entry is owned by the host. It is important that the host sets the
RDY bit of the first buffer of a packet before setting the OWN bit of its packet-segmentation-ring entry.
The 32-bit, single and multiple data-phase PCI accesses are used by the TNETA1570 for buffer and DMA
initialization information. After establishing a buffer address to acquire cell-payload data, the 4-byte ATM header
contained in the DMA entry is loaded into the internal transmit FIFO. The EOP bit in the ATM header is set for
the last cell of AAL5 packets and PTI-based transparent packets. If the EOP status in the DMA entry is cleared
and the current-data-byte count is greater than or equal to 48, a 48-byte PCI-bus read is used to send the
cell-payload contents to the transmit FIFO. If the EOP status in the DMA channel is cleared and the
current-data-byte count is less than 48, the remaining bytes are acquired from the data buffer. The next data
buffer is obtained using the next buffer-address field in the TX DMA state table. If segmentation is occurring on
an EOP buffer, the TNETA1570 performs a PCI-bus read equal to the current-data-byte count acquiring cell
payload and providing byte pad as required.
At the end of a segmentation cycle for a single buffer that is not the end of a packet, the TX DMA state table
entries for current-data-byte count and current-buffer address are modified to show the number of bytes
remaining in the buffer and the starting location for the next ATM-payload fill. The 64-bit, if allowed, or 32-bit
multiple data-phase PCI accesses are used by the TNETA1570 for acquiring ATM payload.
When the AAL5 indicator is set in the TX DMA state table entry, the AAL5 PDU pad and trailer are added to the
last cell(s) by the TNETA1570. As each 64-bit ATM-payload word is loaded in the transmit FIFO, a 32-bit CRC
is calculated with the generator polynomial x^32 + x^26 + x^23 + x^22+ x^16 + x^12+ x^11 + x^
10 + x^8 + x^ 7 + x^ 5 + x^4 + x^2 + x +^1. The AAL5-packet length is also calculated on the number
of nonpad bytes in the AAL5 SDU for each ATM-payload fill. At the end of each AAL5-segmentation cycle for
a single cell, the partial CRC and current AAL5-packet length are updated in the TX DMA state table entry. In
many cases, pad bytes (all 0) must be added after the AAL5 SDU and before the AAL5 trailer to complete cells.
The 32-bit CRC is also calculated using the pad bytes and the control and length fields of the trailer.
Upon processing an AAL5 packet where the current-data-byte count of the last cell in an EOP buffer is between
0 and 40 bytes, pad bytes ( all 0 )are added up to the 40th payload octet. The AAL5-control field, CPCS-UU and
CPI octets, stored in the TX DMA state table entry are packed in payload octets 41 and 42, and the AAL5
length-field calculated across the SDU (not including the pad) is placed in octets 43 and 44. The 32-bit CRC
for the PDU calculated across the packet data, pad, control, and length fields is inverted and placed in octets
44 through 48. For the last cell in an EOP buffer, which is filled with exactly 40 bytes from the segmentation buffer,
no pad is added. After processing the last cell of the packet, the DMA ACT bit is cleared.
When processing a cell in the last buffer of an AAL5 packet with the current-data byte-count field in the TX DMA
state table entry between 41 and 48 bytes, the pad is added up to the 48th octet. The segmentation unit creates
an empty cell including the 8-byte AAL5 trailer. The current-data-byte count in the TX DMA state table entry is
set to zero, but the ACT bit remains set.
Two methods are available for transmitting a transparent-AAL packet. The first method is basically the same
as the procedure for transmitting an AAL5 packet, except that no 8-byte trailer (control, length, and 32-bit CRC)
is generated and transmitted. The TNETA1570 adds any padding necessary to complete the 48-byte cell
payload. The last cell in the transparent-AAL packet has the PTl bits modified to indicate that this is the last cell
in the packet, (i.e., the PTI bits is set to 0 × 1). Abort processing is disabled for transparent-AAL packets.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
21