TNETA1570 Datasheet, PDF (35/68 Pages) Texas Instruments – ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE

TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64ĆBIT PCIĆHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
PRINCIPLES OF OPERATION
transmit loopback
The ability to loopback the segmentation operation to the reassembly operation is helpful in system debug and
verification. This feature is enabled through a bit in the configuration register. It is important to follow the
procedure described below to ensure error-free operation.
The transmit outputs are disabled during loopback to prevent the transfer of data to the downstream element
during testing. The receiver inputs are ignored when loopback is enabled. To place the TNETA1570 in loopback
mode, a device-software reset should be executed to place the SAR in a known state. After reset is executed
(ten clock cycles), the LOOP_BACK bit is set by the host in the configuration register. In a following write
instruction by the host to the configuration register, the EN_TX and EN_RX bits can be set. It is important to set
the EN_TX and EN_RX bits in separate write instructions from the LOOP_BACK bit to allow a clock exchange
for the reassembly UTOPIA bus.
After loopback-mode testing is complete, the device should be reset again before resuming normal operation.
In loopback mode, the UTOPIA bus clock for the segmentation side of the device is also used to internally control
the reassembly-side UTOPIA clock. This allows loopback operation when the two external clocks operate
asynchronously.
reassembly operation
The receive circuitry provides support for the simultaneously reassembly of 30720 packets, hardware timers
for packet aging, and receive-buffer chaining.
receive VPI/VCI DMA pointer table
Addressing
Size
Control-memory address 01000 −01FFF. The VPI field of the incoming ATM cell is
used as address to the entry, thereby initiating the reassembly engine.
Logical entries: 4096
32-bit words: 4096
The receive VPI/VCI DMA pointer table resides in control memory and is used to assign a receive DMA
state-table entry to an incoming virtual connection. The VPI index from the header of an incoming cell is used
to form the address for the VPI/VCI DMA pointer-table entry. The VPI/VCI DMA pointer-table entry contains the
range of VCls that are currently active for that particular VPI index, as well as a base pointer to the receive DMA
state table. If the VCI index of the incoming cell is outside the range of VCls currently active for the corresponding
VPI, the cell is dropped, the VPI/VCI index is captured in the receive-unknown register, and an interrupt is
generated (the interrupt may be masked through the interrupt-mask register). If the VCI index of the incoming
cell is within the range of VCIs currently active for the corresponding VPI, the VCI index is shifted left three bits
and added to the base pointer to obtain the address of the receive DMA state-table entry assigned to that
particular virtual connection. Since there are 12 VPI bits in an ATM header, this table contains 4096 entries. The
entries in the RX VPI/VCI DMA pointer table must be initialized by the host at startup and are shown below:
ENTRY
Word 0
DESCRIPTION
Control, base pointer, VCI range
The definitions of the fields inside each word are as follows:
word 0
Enable (bit 31) Base Pointer (bits 30 −16) Valid VCI Range (bits 15 −0)
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