TNETA1570 Datasheet, PDF (36/68 Pages) Texas Instruments – ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE

TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64ĆBIT PCIĆHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
PRINCIPLES OF OPERATION
enable (bit 31)
This bit is set by the host indicating that packets can be received on this VPI channel. When this bit is cleared,
packets received on this VPI channel are dropped.
base pointer (bits 30 −16)
This field is initialized by the host indicating the base address of the area in the RX DMA state table in control
memory assigned to this VPI channel. The value in this field is used together with the valid VCI range (next entry
in this register) to form the address in the RX DMA state table. Valid values are 800 −7FFF(h).
valid VCI range (bits 15 −0)
This field contains the upper value of the range of the VCI channels that can be received on this VPI channel.
The lower value of the range is always zero. The VCI value of the incoming cell is compared with this field. If
this value is less then or equal to the valid VCI range, the cells for this VCI are accepted. The VCI is masked
before it is compared. Valid values are 0 − F00(h).
The address to the RX DMA state table is calculated as follows:
[[(base pointer + VCI value of incoming cell + value at base register 0) × 8] × 4] (i.e., shift left five times).
This value never exceeds the value of the maximum address in the control-memory map.
VCIs causing values greater than the value of the maximum address in the control-memory map can be
transferred to the data buffers if a VCI mask is used, which reduces the value used by the reassembly engine
to a value less than the maximum control-memory address.
receive DMA state table
Addressing
Size
Control-memory address 04000 −3FFFF. The VCI value of the incoming ATM cell
combined with the value of the entry in the RX VPI/VCI pointer table is used to form
the address.
Max logical entries: 30720
Max 32-bit words: 245760
Min logical entries: 1
Min 32-bit words: 8
The receive DMA state table resides in control memory and contains 30720 entries, allowing for the
simultaneous reassembly of 30720 packets. Each state entry contains eight 32-bit words. The receive DMA
state table has several entries that must be initialized, including whether that particular state is on or off, etc.
The entries in the receive DMA state table are shown below.
ENTRY
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
DESCRIPTION
Control field, EFCN cell counter, packet length
Current buffer address
Start-of-buffer address
Current transparent-AAL packet counter, current buffer length
Start-of-packet pointer
Partial AAL5 receive CRC
On filter bit, FIFO/RX free-buffer ring-pointer table entry
Time-out value, current time-out count
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