TM4C1236D5PM Datasheet, PDF (456/1234 Pages) Texas Instruments – Tiva Microcontroller

System Exception Module
Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), offset
0x008
The SYSEXCMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
System Exception Masked Interrupt Status (SYSEXCMIS)
Base 0x400F.9000
Offset 0x008
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
6
5
4
3
2
1
0
FPIXCMIS FPOFCMIS FPUFCMIS FPIOCMIS FPDZCMIS FPIDCMIS
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
Bit/Field
31:6
5
4
3
Name
reserved
FPIXCMIS
FPOFCMIS
FPUFCMIS
Type
RO
RO
RO
RO
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Floating-Point Inexact Exception Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to an inexact
exception.
This bit is cleared by writing a 1 to the FPIXCIC bit in the SYSEXCIC
register.
0
Floating-Point Overflow Exception Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to an overflow
exception.
This bit is cleared by writing a 1 to the FPOFCIC bit in the SYSEXCIC
register.
0
Floating-Point Underflow Exception Masked Interrupt Status
Value Description
0 An interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to an underflow
exception.
This bit is cleared by writing a 1 to the FPUFCIC bit in the SYSEXCIC
register.
456
June 12, 2014
Texas Instruments-Production Data