TM4C1236D5PM Datasheet, PDF (157/1234 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1236D5PM Microcontroller
Register 70: System Control (SYSCTRL), offset 0xD10
Note: This register can only be accessed from privileged mode.
The SYSCTRL register controls features of entry to and exit from low-power state.
System Control (SYSCTRL)
Base 0xE000.E000
Offset 0xD10
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SEVONPEND reserved SLEEPDEEP SLEEPEXIT reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RO
RW
RW
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:5
4
3
2
Name
reserved
SEVONPEND
reserved
SLEEPDEEP
Type
RO
RW
RO
RW
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Wake Up on Pending
Value Description
0 Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded.
1 Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.
When an event or interrupt enters the pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for an
event, the event is registered and affects the next WFE.
The processor also wakes up on execution of a SEV instruction or an
external event.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Deep Sleep Enable
Value Description
0 Use Sleep mode as the low power mode.
1 Use Deep-sleep mode as the low power mode.
June 12, 2014
157
Texas Instruments-Production Data