LM3S3654 Datasheet, PDF (456/963 Pages) Texas Instruments – Stellaris® LM3S3654 Microcontroller

General-Purpose Timers
10.3.2.5
PWM Mode
Note: The prescaler is not available in 16-Bit PWM mode.
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
16-bit down-counter with a start value (and thus period) defined by the GPTMTnILR register. In this
mode, the PWM frequency and period are synchronous events and therefore guaranteed to be
glitch free. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1,
the TnCMR bit to 0x0, and the TnMR field to 0x1 or 0x2. Table 10-9 on page 456 shows the values
that are loaded into the timer registers when the timer is enabled.
Table 10-9. Counter Values When the Timer is Enabled in PWM Mode
Register
GPTMTnR
GPTMTnV
Count Down Mode
GPTMTnILR
GPTMTnILR
Count Up Mode
Not available
Not available
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0 state. On the next counter cycle in periodic mode, the counter reloads its
start value from the GPTMTnILR register and continues counting until disabled by software clearing
the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode.
In this mode, the GPTMTnR and GPTMTnV registers always have the same value.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTMTnMATCHR
register. Software has the capability of inverting the output PWM signal by setting the TnPWML bit
in the GPTMCTL register.
Figure 10-5 on page 457 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMTnILR=0xC350 and the match value is
GPTMTnMATCHR=0x411A.
456
January 21, 2012
Texas Instruments-Production Data