LM3S3654 Datasheet, PDF (183/963 Pages) Texas Instruments – Stellaris® LM3S3654 Microcontroller

Stellaris^® LM3S3654 Microcontroller
5.2.2.1
Reset Sources
The LM3S3654 microcontroller has six sources of reset:
1. Power-on reset (POR) (see page 184).
2. External reset input pin (RST) assertion (see page 184).
3. Internal brown-out (BOR) detector (see page 186).
4. Software-initiated reset (with the software reset registers) (see page 186).
5. A watchdog timer reset condition violation (see page 187).
6. MOSC failure (see page 188).
Table 5-2 provides a summary of results of the various reset operations.
Table 5-2. Reset Sources
Reset Source
Core Reset?
JTAG Reset?
On-Chip Peripherals Reset?
Power-On Reset
Yes
Yes
Yes
RST
Yes
Yes
Yes
Brown-Out Reset
Yes
Yes
Yes
Software System Request
Yes
Yes
Yes
Reset using the SYSRESREQ
bit in the APINT register.
Software System Request
Yes
No
No
Reset using the VECTRESET
bit in the APINT register.
Software Peripheral Reset
No
Yes
Yes^a
Watchdog Reset
Yes
Yes
Yes
MOSC Failure Reset
Yes
Yes
Yes
a. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, in which case, all the bits in the RESC register are cleared except for the POR indicator.
A bit in the RESC register can be cleared by writing a 0.
At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM
Boot Loader or the application in Flash memory by using any GPIO signal as configured in the Boot
Configuration (BOOTCFG) register.
At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always
executed. The boot sequence executed from ROM is as follows:
1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is
mapped to address 0x0.
2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is
compared with the specified polarity. If the status matches the specified polarity, the ROM is
mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader.
January 21, 2012
183
Texas Instruments-Production Data