LM3S3654 Datasheet, PDF (355/963 Pages) Texas Instruments – Stellaris® LM3S3654 Microcontroller

Stellaris^® LM3S3654 Microcontroller
8.3.4.3
8.3.4.4
8.3.4.5
2. Program the alternate channel control word at offset 0x288 according to Table 8-12.
Table 8-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example
Field in DMACHCTL
DSTINC
DSTSIZE
SRCINC
SRCSIZE
reserved
ARBSIZE
XFERSIZE
NXTUSEBURST
XFERMODE
Bits
31:30
29:28
27:26
25:24
23:18
17:14
13:4
3
2:0
Value
0
0
3
0
0
3
63
0
3
Description
8-bit destination address increment
8-bit destination data size
Source address does not increment
8-bit source data size
Reserved
Arbitrates after 8 transfers
Transfer 64 items
N/A for this transfer type
Use Ping-Pong transfer mode
Note:
In this example, it is not important if the peripheral makes a single request or a burst request.
Because the peripheral has a FIFO that triggers at a level of 8, the arbitration size is set to
8. If the peripheral does make a burst request, then 8 bytes are transferred, which is what
the FIFO can accommodate. If the peripheral makes a single request (if there is any data
in the FIFO), then one byte is transferred at a time. If it is important to the application that
transfers only be made in bursts, then the Channel Useburst SET[8] bit should be set in
the DMA Channel Useburst Set (DMAUSEBURSTSET) register.
Configure the Peripheral Interrupt
An interrupt handler should be configured when using μDMA Ping-Pong mode, it is best to use an
interrupt handler. However, the Ping-Pong mode can be configured without interrupts by polling.
The interrupt handler is triggered after each buffer is complete.
1. Configure and enable an interrupt handler for the peripheral.
Enable the μDMA Channel
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 8 of the DMA Channel Enable Set (DMAENASET) register.
Process Interrupts
The μDMA controller is now configured and enabled for transfer on channel 8. When the peripheral
asserts the μDMA request signal, the μDMA controller makes transfers into buffer A using the primary
channel control structure. When the primary transfer to buffer A is complete, it switches to the
alternate channel control structure and makes transfers into buffer B. At the same time, the primary
channel control word mode field is configured to indicate Stopped, and an interrupt is
When an interrupt is triggered, the interrupt handler must determine which buffer is complete and
process the data or set a flag that the data must be processed by non-interrupt buffer processing
code. Then the next buffer transfer must be set up.
In the interrupt handler:
1. Read the primary channel control word at offset 0x088 and check the XFERMODE field. If the
field is 0, this means buffer A is complete. If buffer A is complete, then:
January 21, 2012
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