CC3120 Datasheet, PDF (45/57 Pages) Texas Instruments – SimpleLink Wi-Fi Wireless Network Processor Internet-of-Things Solution for MCU Applications

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CC3120
SWAS034 – FEBRUARY 2017
6.2 PCB Layout Guidelines
This section details the PCB guidelines to speed up the PCB design using the CC3120R VQFN device.
Follow these guidelines ensures that the design will minimize the risk with regulatory certifications
including FCC, ETSI, and CE. For more information, see CC3120 and CC3220 SimpleLink™ Wi-Fi^® and
IoT Solution Layout Guidelines.
6.2.1 General PCB Guidelines
Use the following PCB guidelines:
• Verify the recommended PCB stackup in the PCB design guidelines, as well as the recommended
layers for signals and ground.
• Ensure that the QFN PCB footprint follows the information in Section 8.
• Ensure that the QFN PCB GND and solder paste follow the recommendations provided in CC3120 and
CC3220 SimpleLink™ Wi-Fi^® and IoT Solution Layout Guidelines.
• Decoupling capacitors must be as close as possible to the QFN device.
6.2.2 Power Layout and Routing
Three critical DC-DC converters must be considered for the CC3120R device.
• Analog DC-DC converter
• PA DC-DC converter
• Digital DC-DC converter
Each converter requires an external inductor and capacitor that must be laid out with care. DC current
loops are formed when laying out the power components.
6.2.2.1 Design Considerations
The following design guidelines must be followed when laying out the CC3120R device:
• Route all of the input decoupling capacitors (C11, C13, and C18) on L2 using thick traces, to isolate
the RF ground from the noisy supply ground. This step is also required to meet the IEEE spectral mask
specifications.
• Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power
amplifier supply lines (pin 33, 40, 41, and 42), and all input supply pins (pin 37, 39, and 44).
• Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24).
• Place all decoupling capacitors as close to the respective pins as possible.
• Power budget: The CC3120R device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, and 700
mA for 1.85 V, for 24 ms during the calibration cycle.
• Ensure the power supply is designed to source this current without any issues. The complete
calibration (TX and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms.
• The CC3120R device contains many high-current input pins. Ensure the trace feeding these pins is
capable of handling the following currents:
– PA DCDC input (pin 39) maximum 1 A
– ANA DCDC input (pin 37) maximum 600 mA
– DIG DCDC input (pin 44) maximum 500 mA
– PA DCDC switching nodes (pin 40 and pin 41) maximum 1 A
– PA DCDC output node (pin 42) maximum 1 A
– ANA DCDC switching node (pin 38) maximum 600 mA
– DIG DCDC switching node (pin 43) maximum 500 mA
– PA supply (pin 33) maximum 500 mA
Copyright © 2017, Texas Instruments Incorporated
Applications, Implementation, and Layout
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