CC3120 Datasheet, PDF (24/57 Pages) Texas Instruments – SimpleLink Wi-Fi Wireless Network Processor Internet-of-Things Solution for MCU Applications

CC3120
SWAS034 – FEBRUARY 2017
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4.13.5 Interfaces
This section describes the interfaces that are supported by the CC3120R device:
• Host SPI
• Flash SPI
4.13.5.1 Host SPI Interface Timing
Figure 4-13 shows the Host SPI interface timing diagram.
I2
CLK
I6
I7
MISO
I9
I8
MOSI
Figure 4-13. Host SPI Interface Timing
SWAS032-017
Table 4-10 lists the Host SPI interface timing parameters.
Table 4-10. Host SPI Interface Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
I1
F ⁽¹⁾
I2
t_clk ^{(2) (1)}
I3
t_LP ⁽¹⁾
I4
t_HT ⁽¹⁾
I5
D ⁽¹⁾
I6
t_IS ⁽¹⁾
I7
t_IH ⁽¹⁾
I8
t_OD ⁽¹⁾
I9
t_OH ⁽¹⁾
Clock frequency @ V_BAT = 3.3 V
Clock frequency @ V_BAT ≤ 2.1 V
Clock period
Clock low period
Clock high period
Duty cycle
RX data setup time
RX data hold time
TX data output delay
TX data hold time
50
45%
4
4
20
12
25
25
55%
20
24
MHz
ns
ns
ns
ns
ns
ns
ns
(1) The timing parameter has a maximum load of 20 pF at 3.3 V.
(2) Ensure that nCS (active-low signal) is asserted 10 ns before the clock is toggled. nCS can be deasserted 10 ns after the clock edge.
24
Specifications
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