AMC6821-Q1 Datasheet, PDF (44/54 Pages) Texas Instruments – INTELLIGENT TEMPERATURE MONITOR AND PWM FAN CONTROLLER

AMC6821-Q1
SBAS475 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com
DCY-RAMP Register (Address 0x23, Value After Power-On or Reset = 0x52)
BIT
NAME DEFAULT
DESCRIPTION
7
RAMPE
0
Ramp Enable Bit. Ignored in software-RPM control.
When RAMPE = 1, Ramp is enabled. The DCY changes to the desired value gradually according
to STEP bits and RATE bits.
When RAMPE = 0, Ramp is disabled. DCY changes to the desired target value immediately.
Default = 0.
6
STEP1
1
Adjustment Step Bits.
5
STEP0
0
STEP1
STEP0
Max Adjustment
0
0
1/256
0
1
2/256
1
0
4/256 (Default)
1
1
8/256
4
RATE2
1
DCY Updating Rate Bits in Auto Temp-Fan Control Mode.
3
RATE1
0
RATE2
RATE1
RATE0
DCY Updates/Sec
(Auto Temp-Fan CTR)
2
RATE0
0
0
0
0
0.0625
0
0
1
0.125
0
1
0
0.25
0
1
1
0.5
1
0
0
1 (Default)
1
0
1
2
1
1
0
4
1
1
1
8
1
THRE1
1
Adjustment Threshold Bits in Auto Temp-Fan Control Mode.
0
THRE0
0
THRE1
THRE0
Threshold
0
0
1/256
0
1
2/256
1
0
3/256 (Default)
1
1
4/256
This register is ignored in the software DCY control mode. This register determines how fast the PWM duty cycle
is adjusted to the desired value when the temperature changes in the automatic temperature-fan control, or when
the fan speed varies from the predetermined value in the software RPM control mode.
RAMPE: Ramp Enable bit.
This bit is ignored in the software RPM control mode. The duty cycle always gradually ramps to the target value
in Software-RPM mode.
Adjustment Step Bits: [STEP1:STEP0]
In the software RPM control, these bits specify the amount that duty cycle changes each time.
In the auto fan temperature control mode, these bits are ignored when RAMPE = 0. When RAMPE = 1, these
bits define the maximum amount that the duty cycle can change each time if the duty cycle needs to be adjusted.
For example, if the current value of the duty cycle is 50% and the desired value is 75%, the total required
increment is 25%. If the step is 1/256 (bits [STEP1:STEP0] = '00'), then the duty cycle increases by 1/256
(0.39%) each time the duty cycle is updated, and the duty cycle reaches the desired value (75%) after 64
updates. This takes eight seconds if the update rate is 8/sec (bits [RATE2:RATE0] = '111'), and takes 64
seconds if the update rate is 1/sec. (bits [RATE2:RATE0] = '100'). However, if the step is 2/256, then the time
reduces to half. If the required adjustment is less than the value specified by step bits, the actual required value
is used. For example, if the current duty cycle is 50%, the required value is 73%, and the step is 4/256, a total of
15 updates are needed. The duty cycle increases 21.875% after the first 14 updates, and increases 1.125% in
the last update.
44
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