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TLC320AD90C Datasheet, PDF (43/51 Pages) Texas Instruments – Stereo Audio Codec | |||
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3.4.3 Data Setup and Hold Timing
PARAMETER
tsu1 Setup time, SDATA_IN, SDATA_OUT, SYNC valid to BIT_CLKâ
th1 Hold time, BIT_CLKâ to SDATA_IN, SDATA_OUT, SYNC invalid
MIN TYP MAX UNIT
15
ns
5
ns
3.4.4 Signal Rise and Fall Timing
PARAMETER
tr(CLK)
tf(CLK)
tr(DIN)
tf(DIN)
tr(DOUT)
tf(DOUT)
tr(SYNC)
tf(SYNC)
Rise time, BIT_CLK
Fall time, BIT_CLK
Rise time, SDATA_IN
Fall time, SDATA_IN
Rise time, SDATA_OUT
Fall time, SDATA_OUT
Rise time, SYNC
Fall time, SYNC
MIN TYP MAX UNIT
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
2
6 ns
3.4.5 Warm/Cold Reset Timing, TA = 25°C, AVDD = DVDD = 5 V dc,
AVSS = DVSS = 0 V, 50-pF External Load
PARAMETER
MIN TYP MAX UNIT
twL(RST)
td(RST_CLK)
Pulse width, RESET low
Delay time, RESETâ to BIT_CLKâ
1
ms
162.8
ns
PARAMETER
twH(SYNC)
Pulse width, SYNC high
td(SYNC_CLK) Delay time, SYNCâ to BIT_CLKâ
MIN
1
162.8
TYP MAX UNIT
1.3
ms
ns
3.4.6 ATE Test Mode Timing, TA = 25°C, AVDD = DVDD = 5 V dc,
AVSS = DVSS = 0 V, 50-pF External Load
PARAMETER
MIN TYP MAX UNIT
tsu3
Setup time, SDATA_OUTâ, SYNC to RESETâ (see Notes 17
and 18)
15
ns
td(off)
Delay time, RESETâ to SDATA_IN, BIT_CLK Hi-Z (see
Notes 17 and 18)
25 ns
NOTES: 17. All AC-Link signals are normally low though RESETâ. SDATA_OUT should be high prior to RESETâ which
causes the TLC320AD90C AC-Link outputs to go high impedance which is suitable for ATE in circuit
testing.
18. The Texas Instruments internal test mode is entered by bringing SYNC high prior to RESETâ. This mode
has no effect on the TLC320AD90C AC-Link output signal levels.
3â8
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