TLC320AD90C Datasheet, PDF (17/51 Pages) Texas Instruments – Stereo Audio Codec

2.2.2.2 SYNC
The TLC320AD90C SYNC signal includes the following characteristics:
• SYNC is driven by the controller
• SYNC is derived by dividing down the BIT_CLK signal (BIT_CLK is an input to the controller)
• SYNC is high for 16 BIT_CLKs at the beginning of each frame. These 16 BIT_CLKs (bits) define
the TAG phase. The TAG phase defines the beginning of a frame.
• The TLC320AD90C synchronizes data conversion with the rising edge of SYNC
• SYNC remains low for the next 240 BIT_CLKs. These 240 BIT_CLKs (bits) define the DATA
phase.
• SYNC is sampled by TLC320AD90C at the falling edge of BIT_CLK
• SYNC transition edges are on the rising edge of BIT_CLK
• The controller must hold SYNC low during a TLC320AD90C power-down halted state
2.2.2.3 BIT_CLK
The TLC320AD90C BIT_CLK signal includes the following characteristics:
 • BIT_CLK is fixed at 12.288 MHz (256 sampling rate). The sampling rate is fixed at 48 kHz.
• BIT_CLK is sourced by the TLC320AD90C
• BIT_CLK goes low and remains low when a write to register 26h with PR4 is detected
(power-down state)
• BIT_CLK becomes active from a power-down state in response to a cold or warm TLC320AD90C
reset condition
2.2.2.4 SDATA_OUT
The TLC320AD90C SDATA_OUT signal includes the following characteristics:
• SDATA_OUT is driven by the controller
• SDATA_OUT transitions on the rising edge of BIT_CLK
• SDATA_OUT is captured by the TLC320AD90C on the falling edge of BIT_CLK
• The controller must hold SDATA_OUT low during an TLC320AD90C power-down halted state
2.2.2.5 SDATA_IN
The TLC320AD90C SDATA_IN signal includes the following characteristics:
• SDATA_IN is driven by the TLC320AD90C
• SDATA_IN transitions on the rising edge of BIT_CLK
• SDATA_IN is captured by the controller on the falling edge of BIT_CLK
• SDATA_IN goes low and remains low when a write to register 26h with PR4 is detected
(power-down state)
• SDATA_IN becomes active from a power-down state in response to a cold or warm
TLC320AD90C reset condition
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