LP3925 Datasheet, PDF (42/51 Pages) Texas Instruments – High Performance Power Management Unit for Handset Applications

Reference Output
Reference Output Reference output voltage is used by the
external blocks (plug-in microphone, ADCs, etc). This voltage
is achieved by the reference buffer and is supplied to the
REF_OUT bump. Reference buffer has a load capability of
1mA and when not used can be disabled while the output is
pulled by an internal resistor to the ground. A presented dia-
gram shows a typical application of REF_OUT signal for
battery temperature measurement purpose, using an internal
battery thermistor.
30120436
FIGURE 23. Typical REF_OUT Battery
Temperature Measurement
Application Diagram
REFERENCE BUFFER ELECTRICAL CHARACTERISTICS
Typical values and limits appearing in normal type apply for T_J = 25ºC. Limits appearing in boldface type apply over the entire
junction temperature range for operation, T_J = −40°C to +125°C. Unless otherwise specified, the following applies for V_BATT = 3.6V.
(Note 6)
Symbol
Parameter
Conditions
Typ.
Limits
Min
Max
Units
V_REF
I_LOAD
R_{PULL_DOWN}
Reference voltage accuracy ^{ILOAD = 0mA}
I_LOAD = 1mA
Load Current
Integral Nonlinearity
0.3
%
1
−1
+1
mA
400
kΩ
UVLO Operation
UVLO measures system voltage on pin VDD and compares
it to selected voltages. The function uses 2 comparators,
which are configured in register address 0x85 (possible val-
ues are stated in the table below). These comparators are
combined into UVLO_N state, which can affect startup, cause
shutdown or generate interrupt. The state is readable in reg-
ister address 0x8E bit 2.
UVLO_N state can change on following conditions:
• If system voltage is lower than UVLO LEVEL1 and UVLO
LEVEL2, then UVLO_N state is set to '0'.
• If system voltage is higher than UVLO LEVEL1 and UVLO
LEVEL2, then UVLO_N state is set to '1'.
Using different values for levels 1 and 2 provides a window
for voltage drops under high load working conditions.
UVLO_N state '0' indicates that the voltage is below normal
working range, so the system is not allowed to start up. This
state can also cause the system to shut down. UVLO_N state
'1' indicates that the voltage is in normal working range, so
the system is allowed to start up and operate. State transition
'1'->'0' causes an UVLO interrupt, which can be sent to IRQ_N
output.
Current Sinks
LP3925 provides 3 current sinks, which can sink current for
LEDs, vibration motors or other external functions. Current
sinks have selectable DC current value and also PWM control
options. SINK1, SINK2 and SINK3 are multifunction pins, so
current sink function and DC current value are selectable with
respective GPIO control bits (described in the table in Multi-
functional pins section). SINK1 has a 250 mA maximum
current value, SINK2 and SINK3 provide up to 100 mA. If the
pin is configured as a current sink with a certain current, then
PWM CODE bits will switch that current on and off, according
to the PWM algorithm.
The smallest unit in PWM control is a time slot. The length of
a time slot is set with ISINK PWM TIME SLOT SIZE bits.
Smaller time slot causes faster switching, but increases non-
linearity. 7 time slots form a PWM cycle. Cycle is the current
sink on-off switching period, so the main PWM frequency can
be calculated as: Fpwm = 1/(7*Ttimeslot).
9 cycles, which is 9*7=63 time slots, form a PWM pattern.
ISINK PWM CODE bits select, during how many of these 63
time slots the current sink is active. Code 000000 means that
the sink is always off. Code 111111 (63 in decimal) means
that the sink is always on.
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