LP3925 Datasheet, PDF (14/51 Pages) Texas Instruments – High Performance Power Management Unit for Handset Applications

Enable Control
LP3925 provides much flexibility in enabling/disabling on-chip
features. The blocks that have advanced enable controls in-
clude: LDOs, buck regulators, USB transceiver, TCXO
buffers, SIM level shifter. Each block has a 4-bit code in reg-
isters, which selects the enable signal for that block. These
codes are in register addresses 0x37...0x41, with bit names
ending with CONTROL. The enable signal translation table is
stated below.
In order to make the control more flexible, there is a possibility
for the blocks to be enabled through registers 0x00…0x02 or
through multifunctional pins. One control signal can enable
any number of features. This allows to group signals so, that
any end-system function can be switched on with only one
input or register write.
There are additional enable controls for sleep mode operation
with ALLOW IN SLEEP bits in register addresses
0x34...0x36. If a block is not allowed in sleep mode, then this
block is always off during sleep. If a block is allowed in sleep
mode, then it is controlled by its selected enable signal, and
does not depend on sleep mode.
Example 1:
Goal: Buck2 is always disabled in sleep mode and enabled
in idle mode.
Best solution: write BUCK2 CONTROL to '0001' and AL-
LOW BUCK2 IN SLEEP to '0'; now Buck2 is enabled in
working mode and disabled in sleep mode, with no separate
enable bit/input.
Example 2:
Goal – Enable LDO9, LDO10 and TCXO buffer1 together
with one register write.
One possible solution: write LDO9 CONTROL, LDO10
CONTROL and TCXO1 CONTROL to 0010; now writing '11'
to address 0x00 bits [1:0] enables all three blocks.
Multifunctional Pins
Some pins corresponding to 32 kHz oscillator, USB transceiv-
er, SIM interface, TCXO buffer, current sink and comparator
blocks along with RSENSE pin are multifunctional pins, which
means that they can be programmed as analog function pins,
ADC inputs or digital input/output pins. These pins can be
configured from registers 0x19..0x23.
If one block uses more than one pin, then all the pins must be
configured for the block to work. For example, all 6 SIM level
shifter pins must have level shifter function selected, before
the block is connected to the pins. To use USB with 4- or 5-
wire interface, the used pins must all be configured as 5-wire
USB pins. For 3-wire interface the 3 pins must all be config-
ured as 3-wire USB pins.
Some GPIO functions have separate enable controls. These
enables will take the blocks to a shutdown state, but will not
disconnect them from the pins. The GPIO configuration op-
tions are described in the table below.
Pin/Code
OSC_32 KHZ
RSENSE
SIM_RST_IN
SIM_CLK _IN
SIM_DATA
SIM_RST
SIM_CLK
SIM_IO
TCXO1_I
TCXO1_O
TCXO2_I
TCXO2_O
OE_N
DATA/VP
SEO/VM
RCV
SPND
INP1
INP2
1000
1001
1010
1011
1100
1101
1110
1111
32 kHz OSC
Maximum measurable voltage drop on sense resistor
N/A
12 mV
26.4 mV
39.6 mV
56.4 mV
81.6 mV
98.4 mV 120 mV
SIM RST, baseband side
SIM CLK, baseband side
SIM I/O, baseband side
SIM RST, SIM side
SIM CLK, SIM side
SIM I/O, SIM side
TCXO1 warmup time before output enable
1µs
21 µs
41 µs
61 µs
TCXO1 output driver strength
x8
x4
x2
x1
TCXO2_I warmup time before output enable
TCXO2in wait=1µs
TCXO2in wait=21 µs
TCXO2in wait=41 µs
TCXO2in wait=61 µs
TCXO2 output driver strength
TCXO2out strength=1 TCXO2out strength=2
TCXO2out strength=4
TCXO2out strength=8
OE_N: 3-pin USB interface
OE_N: 5-pin USB interface
DATA: 3-pin USB interface
VP: 5-pin USB interface
SEO: 3-pin USB interface
VM: 5-pin USB interface
N/A
RCV: 5-pin USB interface
N/A
SUSP: 5-pin USB interface
Comparator1 input comparison threshold
0.4V
0.6V
0.8V
1.0V
1.2V
1.5V
1.8V
2.4V
Comparator2 input comparison threshold
0.4V
0.6V
0.8V
1.0V
1.2V
1.5V
1.8V
2.4V
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