ADS54J54 Datasheet, PDF (42/66 Pages) Texas Instruments – Quad Channel 14-Bit 500 MSPS ADC

ADS54J54
SLASE67 – JANUARY 2015
7.6.1.6 Register Address 6
Figure 78. Register Address 6, Reset: 0xFFFF, Hex = 6
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
ANALOG SLEEP MODES – SPI
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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D0
1
Bit
D15:D1
D13
D11
D9
D7
D6
D4
D3
D2
D1
D0
Table 14. Register Address 6 Field Descriptions
Field
Type
ANALOG SLEEP MODES – SPI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
1
1
Description
Power-down function controlled via SPI. When a bit is set to 0,
the function is powered down when ENABLE pin is high.
However, register 0x05 has higher priority. For example, if D13
(deep sleep channel A) in 0x05 is enabled, it cannot be powered
down with the SPI.
Light sleep channel A
Light sleep channel B
Light sleep channel C
Light sleep channel D
Temperature sensor
Clock buffer
Clock divider channel AB
Clock divider channel CD
Buffer SYSREFAB
Should be left set to 1
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0000 0000 0000 000
1000 0000 0000 000
1000 0000 0001 111
1010 1010 1001 111
1111 1111 1111 111
Table 15. Configurations When ENABLE Pin is High
Global power down
Standby
Deep sleep
Light sleep
Normal operation
Description
Control power down function through ENABLE pin:
1. Configure power-down mode in register 0x05
2. Normal operation: ENABLE pin high
3. Power-down mode: ENABLE pin low
Control power down function through SPI (ENABLE pin always high):
1. Assign power-down mode in register 0x06
2. Normal operation 0x06 is 0xFFFF
3. Power-down mode: configure power down mode in register 0x06
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