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| ADS54J54 Datasheet, PDF (3/66 Pages) Texas Instruments – Quad Channel 14-Bit 500 MSPS ADC | |||
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5 Pin Configuration and Functions
ADS54J54
RGC 64 Pin Package
Top View
ADS54J54
SLASE67 â JANUARY 2015
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SDOUT 1
48 SYNCbABM
SDATA 2
47 SYNCbABP
SCLK 3
SDENb 4
SYSREFABM 5
46 DB0P
45 DB0M
44 IOVDD
SYSREFABP 6
43 DB1P
AVDDC 7
42 DB1M
CLKINM 8
41 PLLVDD
CLKINP 9
40 PLLVDD
AVDDC 10
39 DD1M
SYSREFCDP 11
38 DD1P
SYSREFCDM 12
37 IOVDD
SRESETb 13
36 DD0M
ENABLE 14
VREF 15
GND PAD (backside)
35 DD0P
34 SYNCbCDP
VCM 16
33 SYNCbCDM
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN
NAME
NO.
INPUT OR REFERENCE
INAP, INAM
63, 62
INBP, INBM
58, 59
INCP, INCM
18, 19
INDP, INDM
23, 22
VCM
16
VREF
15
CLOCK/SYNC
CLKINP,
CLKINM
9, 8
SYSREFABP,
SYSREFABM
6, 5
SYSREFCDP,
SYSREFCDM
11, 12
Pin Functions
I/O
DESCRIPTION
I Differential analog input for channel A
I Differential analog input for channel B
I Differential analog input for channel C
I Differential analog input for channel D
O Common mode output voltage to bias analog inputs, Vcm = 2.0 V
O Voltage reference output. A 0.1-µF bypass capacitor to ground close to the pin is recommended
I Differential clock input for channel
I LVDS input with internal 100-Ω termination. External SYSREF input for channels A, B, C, and D
I
LVDS input with internal 100-Ω termination. External SYSREF input for channels C and D if output
rate of channel A/B is different from channel C/D.
Copyright © 2015, Texas Instruments Incorporated
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