ADS54J54 Datasheet, PDF (1/66 Pages) Texas Instruments – Quad Channel 14-Bit 500 MSPS ADC

Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
ADS54J54 Quad Channel 14-Bit 500 MSPS ADC
ADS54J54
SLASE67 – JANUARY 2015
1 Features
•1 4 Channel, 14-Bit 500 MSPS ADC
• Analog Input Buffer with High Impedance Input
• Flexible Input Clock Buffer With Divide by 1/2/4
• 1.25 V_PP Differential Full-Scale Input
• JESD204B Serial Interface
– Subclass 1 compliant up to 5 Gbps
– 1 Lane Per ADC up to 250 Msps
– 2 Lanes Per ADC up to 500 Msps
• 64-Pin QFN Package (9 mm x 9 mm)
• Key Specifications:
– Power Dissipation: 875 mW/ch
– Input Bandwidth (3 dB): 900 MHz
– Aperture Jitter: 98 fs rms
– Channel Isolation: 85 dB
– Performance at ƒ_in = 170 MHz at 1.25 V_PP,
1lane 2x Decimation –1 dBFS
– SNR: 67.2 dBFS
– SFDR: 85 dBc HD2,3; 95 dBFS non-HD2,3
– Performance at ƒ_in = 370 MHz at 1.25 V_PP,
2lane no Decimation –1 dBFS
– SNR: 64.7 dBFS
– SFDR: 75 dBc HD2,3; 83 dBFS non-HD2,3
2 Applications
• Multi-Carrier, Multi-Mode, Multi-Band Cellular
Receivers
– TDD-LTE, FDD-LTE, CDMA, WCMDA,
CMDA2k, GSM
• Microwave Backhaul
• Wireless Repeaters
• Distributed Antenna Systems (DAS)
• Broadband Wireless
• Ultra-Wide Band Software Defined Radio
• Data Acquisition
• Test and Measurement Instrumentation
• Signal Intelligence and Jamming
• Radar and Satellite Systems
• Cable Infrastructure
3 Description
The ADS54J54 is a low power, wide bandwidth 14-bit
500 MSPS quad channel analog-to-digital converter
(ADC). It supports the JESD204B serial interface with
data rates up to 5 Gbps supporting 1 or 2 lanes per
ADC. The buffered analog input provides uniform
input impedance across a wide frequency range while
minimizing sample-and-hold glitch energy. A
sampling clock divider allows more flexibility for
system clock architecture design. The ADS54J54
provides excellent spurious-free dynamic range
(SFDR) over a large input frequency range with very
low power consumption. Optional 2x Decimation Filter
provides high-pass or low-pass filter modes.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADS54J54
VQFN (64)
9.00mm x 9.00mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
INAP/M
INBP/M
SYSREFABP/M
CLKINP/M
SYSREFCDP/M
14-bit
ADC
14-bit
ADC
Digital Block
Optional 2x
Decimination
Digital Block
Optional 2x
Decimination
JESD204B
JESD204B
Divide by
1, 2, 4
PLL
x10/x20
INCP/M
INDP/M
VCM
Common
Mode
14-bit
ADC
14-bit
ADC
Digital Block
Optional 2x
Decimination
Digital Block
Optional 2x
Decimination
JESD204B
JESD204B
OVRA
DA[0,1]P/M
DB[0,1]P/M
OVRB
SYNCbAB
SYNCbCD
OVRC
DC[0,1]P/M
DD[0,1]P/M
OVRD
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.