ADS54J54 Datasheet, PDF (23/66 Pages) Texas Instruments – Quad Channel 14-Bit 500 MSPS ADC

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7 Detailed Description
ADS54J54
SLASE67 – JANUARY 2015
7.1 Overview
The ADS54J54 is a low power, wide bandwidth 14-bit 500 MSPS quad channel ADC. It supports the JESD204B
serial interface with data rates up to 5.0 Gbps supporting 1 or 2 lanes per channel. The buffered analog input
provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch
energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS54J54
provides excellent SFDR over a large input frequency range with low power consumption.
7.2 Functional Block Diagram
INAP/M
INBP/M
SYSREFABP/M
CLKINP/M
SYSREFCDP/M
14-bit
ADC
14-bit
ADC
Digital Block
Optional 2x
Decimination
Digital Block
Optional 2x
Decimination
JESD204B
JESD204B
Divide
by 1,2,4
PLL
x10/x20
INCP/M
INDP/M
VCM
Common
Mode
14-bit
ADC
14-bit
ADC
Digital Block
Optional 2x
Decimination
Digital Block
Optional 2x
Decimination
JESD204B
JESD204B
OVRA
DA[0,1]P/M
DB[0,1]P/M
OVRB
SYNCbAB
SYNCbCD
OVRC
DC[0,1]P/M
DD[0,1]P/M
OVRD
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