BQ40Z50-R2 Datasheet, PDF (41/51 Pages) Texas Instruments – 1-Series, 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager

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bq40z50-R2
SLUSCS4 – JUNE 2017
Layout Guidelines (continued)
11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
Use wide copper traces to lower the inductance of the bypass capacitor circuit. Figure 47 shows an example
layout, demonstrating this technique.
C2
C3
F1
Pack+
Low Level Circuits
BAT+
C2 C3
Q2
Q1
F1
C1
Pack±
C1
J1
R1
BAT±
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Figure 47. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3
11.1.2 ESD Spark Gap
Protect SMBus clock, data, and other communication lines from ESD with a spark gap at the connector. The
pattern in Figure 48 is recommended, with 0.2-mm spacing between the points.
Figure 48. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD
11.2 Layout Example
CHARGE
AND
DISCHARGE
PATH
2^ND LEVEL
PROTECTOR
SENSE
RESISTOR
CURRENT
FILTER
THERMISTORS
LEDS
Figure 49. Top Layer
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