BQ40Z50-R2 Datasheet, PDF (12/51 Pages) Texas Instruments – 1-Series, 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager

bq40z50-R2
SLUSCS4 – JUNE 2017
www.ti.com
ADC (continued)
Typical values stated where T_A = 25°C and VCC = 14.4 V, Min/Max values stated where T_A = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Offset error⁽²⁾
Offset error drift
Gain error
Gain error drift
Effective input resistance
TEST CONDITIONS
16-bit, Post-calibration, V_FS = V_REF1
16-bit, Post-calibration, V_FS = V_REF1
16-bit, –0.1 V to 0.8 × V_FS
16-bit, –0.1 V to 0.8 × V_FS
MIN
TYP
±67
0.6
±0.2%
8
MAX
±157
3
±0.8%
150
UNIT
µV
µV/°C
FSR
PPM/°C
MΩ
(2) For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and V_REF1/2, the offset error is multiplied by (1/ADC
multiplexer scaling factor (K)).
7.17 ADC Digital Filter
Typical values stated where T_A = 25°C and VCC = 14.4 V, Min/Max values stated where T_A = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Single conversion
31.25
Conversion time
Single conversion
Single conversion
15.63
ms
7.81
Single conversion
1.95
Resolution
No missing codes
16
Bits
Effective resolution
With sign, t_CONV = 31.25 ms
With sign, t_CONV = 15.63 ms
With sign, t_CONV = 7.81 ms
With sign, t_CONV = 1.95 ms
14
15
13
14
Bits
11
12
9
10
7.18 CHG, DSG FET Drive
Typical values stated where T_A = 25°C and VCC = 14.4 V, Min/Max values stated where T_A = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Output voltage
ratio
Ratio_DSG = (V_DSG – V_BAT)/V_BAT, 2.2 V < V_BAT < 4.92 V,
10 MΩ between PACK and DSG
Ratio_CHG = (V_CHG – V_BAT)/V_BAT, 2.2 V < V_BAT < 4.92 V,
10 MΩ between BAT and CHG
2.133
2.133
2.333
2.333
2.433
—
2.433
V_(FETON)
V_(FETOFF)
t_R
t_F
Output voltage,
V_DSG(ON) = V_DSG – V_BAT, V_BAT ≥ 4.92 V, 10 MΩ between
PACK and DSG, V_BAT = 18 V
CHG and DSG on _{VCHG(ON) = VCHG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between}
BAT and CHG, V_BAT = 18 V
Output voltage,
V_DSG(OFF) = V_DSG – V_PACK, 10 MΩ between PACK and
DSG
CHG and DSG off
V_CHG(OFF) = V_CHG – V_BAT, 10 MΩ between BAT and CHG
Rise time
V_DSG from 0% to 35% V_DSG(ON)(TYP), V_BAT ≥ 2.2 V, C_L =
4.7 nF between DSG and PACK, 5.1 kΩ between DSG
and C_L, 10 MΩ between PACK and DSG
V_CHG from 0% to 35% V_CHG(ON)(TYP), V_BAT ≥ 2.2 V, C_L =
4.7 nF between CHG and BAT, 5.1 kΩ between CHG
and C_L, 10 MΩ between BAT and CHG
Fall time
V_DSG from V_DSG(ON)(TYP) to 1 V, V_BAT ≥ 2.2 V, C_L = 4.7 nF
between DSG and PACK, 5.1 kΩ between DSG and C_L,
10 MΩ between PACK and DSG
V_CHG from V_CHG(ON)(TYP) to 1 V, V_BAT ≥ 2.2 V, C_L = 4.7
nF between CHG and BAT, 5.1 kΩ between CHG and
C_L, 10 MΩ between BAT and CHG
10.5
11.5
10.5
11.5
–0.4
–0.4
200
200
40
40
12
V
12
0.4
V
0.4
500
µs
500
300
µs
200
12
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